Synthesis tuning system for VLSI design optimization
US-9529951-B2 · Dec 27, 2016 · US
Intra-run design decision process for circuit synthesis
US9690900B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9690900-B2 |
| Application number | US-201514837102-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 27, 2015 |
| Priority date | Jun 30, 2015 |
| Publication date | Jun 27, 2017 |
| Grant date | Jun 27, 2017 |
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Abstract
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A system and method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design are described. The method includes executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, and determining a quality measure associated with each of the two or more scenarios. The method also includes performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design, the method comprising: executing, using a processor, a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters; determining, using the processor, a quality measure associated with each of the two or more scenarios; and performing the intra-run decision using the processor, by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis, the eliminating based on the quality measure associated with each of the two or more scenarios. 2. The method according to claim 1 , further comprising generating the two or more scenarios based on a forking process that includes adding each new scenario specific to the stage to each previous scenario obtained from a previous stage of the synthesis. 3. The method according to claim 1 , wherein the determining the quality measure includes determining a quality of results (QOR) measure. 4. The method according to claim 3 , wherein the determining the QOR measure is based on timing, power consumption, and congestion resulting from each of the two or more scenarios. 5. The method according to claim 1 , wherein the eliminating the one or more of the two or more scenarios includes eliminating any scenario with the associated quality measure below a threshold. 6. The method according to claim 1 , wherein the eliminating the one or more of the two or more scenarios includes comparing the quality measure associated with each of the two or more scenarios with a baseline. 7. The method according to claim 1 , wherein the eliminating the one or more of the two or more scenarios includes eliminating all but a specified number of the two or more scenarios with highest associated quality measures. 8. The method according to claim 1 , further comprising determining a total number of iterations for which to run one of the two or more scenarios based on the quality measure associated with each iteration or a runtime constraint.
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Classifications
Design verification, e.g. functional simulation or model checking · CPC title
- G06F30/398Primary
Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title
Physics · mapped topic
- G06F17/5081Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9690900B2 cover?
- A system and method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design are described. The method includes executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, and determining a quality measure associated with each of the t…
- Who is the assignee on this patent?
- IBM
- What technology area does this patent fall under?
- Primary CPC classification G06F30/398. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jun 27 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).