Intra-run design decision process for circuit synthesis

Patent metadata

Field	Value
Publication number	US-9703920-B2
Application number	US-201514754987-A
Country	US
Kind code	B2
Filing date	Jun 30, 2015
Priority date	Jun 30, 2015
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A system and method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design are described. The method includes executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, and determining a quality measure associated with each of the two or more scenarios. The method also includes performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.

First claim

What is claimed is:

1. A system to perform an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design, the system comprising:
a memory device configured to store instructions and information; and
a processor configured to execute the instructions to execute a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, determine a quality measure associated with each of the two or more scenarios, and perform the intra-run decision to eliminate one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.

2. The system according to claim 1 , wherein the processor generates the two or more scenarios based on a forking process that includes adding each new scenario specific to the stage to each previous scenario obtained from a previous stage of the synthesis.

3. The system according to claim 1 , wherein the processor determines the quality measure as a quality of results (QOR) measure.

4. The system according to claim 3 , wherein the QOR measure is based on timing, power consumption, and congestion resulting from each of the two or more scenarios.

5. The system according to claim 1 , wherein the processor eliminates the one or more of the two or more scenarios based on the associated quality measure of the one or more of the two or more scenarios being below a threshold.

6. The system according to claim 1 , wherein the memory device stores a baseline synthesis result, and the processor eliminates the one or more of the two or more scenarios based on the associated quality measure of the one or more of the two or more scenarios being below a corresponding quality measure in the baseline synthesis result.

7. The system according to claim 1 , wherein the processor eliminates the one or more of the two or more scenarios by eliminating all but a specified number of the two or more scenarios with highest associated quality measures.

8. A computer program product to perform intra-run decision making during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design, the computer program product comprising a non-transitory computer readable storage medium having program code embodied therewith, the program code executable by a processor to perform a method comprising:
executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters;
determining a quality measure associated with each of the two or more scenarios; and
performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.

9. The computer program product according to claim 8 , the method further comprising generating the two or more scenarios based on a forking process that includes adding each new scenario specific to the stage to each previous scenario obtained from a previous stage of the synthesis.

10. The computer program product according to claim 8 , wherein the determining the quality measure includes determining a quality of results (QOR) measure, and the determining the QOR measure is based on timing, power consumption, and congestion resulting from each of the two or more scenarios.

11. The computer program product according to claim 8 , wherein the eliminating the one or more of the two or more scenarios includes eliminating any scenario with the associated quality measure below a threshold, comparing the quality measure associated with each of the two or more scenarios with a baseline, or eliminating all but a specified number of the two or more scenarios with highest associated quality measures.

12. The computer program product according to claim 8 , the method further comprising determining a total number of iterations for which to run one of the two or more scenarios based on the quality measure associated with each iteration or a runtime constraint.

Assignees

• IBM

Inventors

• Berry Christopher J
• Reddy Lakshmi
• Saha Sourav
• Ziegler Matthew M

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/505

  Physics · mapped topic

• G06F17/5081 Primary

  Physics · mapped topic

• G06F17/5022

  Physics · mapped topic