Verification low power collateral generation

Patent metadata

Field	Value
Publication number	US-9785732-B2
Application number	US-201514738487-A
Country	US
Kind code	B2
Filing date	Jun 12, 2015
Priority date	Jun 12, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

Aspects of the present disclosure relate to methods, systems, and computer readable mediums for generating transition state specifications that include information regarding low power behavior of a System on Chip (SoC) and/or a Network on Chip (NoC). Such transition state specifications can enable verification of switching behavior when elements/components of a SoC/NoC or a subset thereof switch from one power profile to another, or when the elements/components switch in stable states of power based on inputs such as voltages, clocks, power domains, and traffic.

First claim

What is claimed is:

1. A method, comprising:
generating a specification comprising information regarding low power behavior of a chip implementing a Network on Chip (NoC), the information configured to provide a function for checking the behavior of the chip for correctness of the NoC for at least one of:
when switching from one power profile comprising a first set of on/off statuses for bridges and routers of the NoC to another power profile comprising a second set of on/off statuses for the bridges and the routers of the NoC, and
in a stable state of a power profile comprising a set of on/off statuses for the bridges and the routers of the NoC from an input comprising parameter information for at least one of: voltage level, clock, power domain, and traffic for the NoC;
wherein the generating the specification comprises generating one or more assertions or invariants in one or more files in a language utilized by a verification methodology applying the function for the checking the behavior of the chip for the correctness of the NoC.

2. The method of claim 1 , wherein the generated specification is configured to support both dynamic and static checks on a design and a power intent of the NoC.

3. The method of claim 1 , wherein the generating the specification is conducted hierarchically, wherein the specification is configured to be represented hierarchically for the NoC.

4. The method of claim 1 , wherein the generated specification is configured to provide the function for checking the correctness of the chip at a unit-level or a full-chip level of the NoC.

5. The method of claim 1 , where the function is configured to check the behavior either within a hardware element or across hardware elements of the NoC.

6. The method of claim 1 , further comprising checking the generated specification for correctness of automatically generated power intent of the NoC, against an original input specification of the NoC.

7. The method of claim 1 , further comprising running a set of tests for the NoC, and determining coverage of conditions met of the set of tests from the generated specification.

8. The method of claim 1 , further comprising utilizing the generated specification to inject events into a design during a hardware simulation for the NoC for one or more conditions.

9. The method of claim 1 , further comprising utilizing the generated specification for checking values for at least one of an interface and a wire for compliance with a protocol specification for the NoC.

10. A non-transitory computer readable medium storing instructions for executing a process, the instructions comprising:
generating a specification comprising information regarding low power behavior of a chip implementing a Network on Chip (NoC), the information configured to provide a function for checking the behavior of the chip for correctness of the NoC for at least one of:
when switching from one power profile comprising a first set of on/off statuses for bridges and routers of the NoC to another power profile comprising a second set of on/off statuses for the bridges and the routers of the NoC, and
in a stable state of a power profile comprising a set of on/off statuses for the bridges and the routers of the NoC from an input comprising parameter information for at least one of: voltage level, clock, power domain, and traffic for the NoC;
wherein the generating the specification comprises generating one or more assertions or invariants in one or more files in a language utilized by a verification methodology applying the function for the checking the behavior of the chip for the correctness of the NoC.

11. The non-transitory computer readable medium of claim 10 , wherein the generated specification is configured to support both dynamic and static checks on a design and a power intent of the NoC.

12. The non-transitory computer readable medium of claim 10 , wherein the generating the specification is conducted hierarchically, wherein the specification is configured to be represented hierarchically for the NoC.

13. The non-transitory computer readable medium of claim 10 , wherein the generated specification is configured to provide the function for checking the correctness of the chip at a unit-level or a full-chip level of the NoC.

14. The non-transitory computer readable medium of claim 10 , where the function is configured to check the behavior either within a hardware element or across hardware elements of the NoC.

Assignees

• Netspeed Systems
• Netspeed Systems Inc

Inventors

• Pusuluri Vishnu Mohan
• Patchamatla Santhosh
• Kaushal Rimu
• Gangwar Anup
• Kumar Sailesh

Classifications

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2217/78

  Physics · mapped topic

• G06F17/5018 Primary

  Physics · mapped topic