System-on-chip intellectual property block discovery

Patent metadata

Field	Value
Publication number	US-9639646-B2
Application number	US-201414338155-A
Country	US
Kind code	B2
Filing date	Jul 22, 2014
Priority date	Jul 22, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

An integrated circuit (IC) includes a bridge circuit configured to receive a first request from an external system, a discover circuit coupled to the bridge circuit and configured to process the first request received from the bridge circuit, and a memory map coupled to the discover circuit. The memory map stores a record for each of a plurality of Intellectual Property (IP) blocks implemented within the IC. The discover circuit is configured to generate a list of the IP blocks implemented within the IC from the records of the memory map responsive to the first request. The bridge circuit is configured to send the list to the external system.

First claim

What is claimed is:

1. An integrated circuit, comprising:
programmable circuitry;
a bridge circuit configured to receive a first request from an external system;
a discover circuit coupled to the bridge circuit and configured to process the first request received from the bridge circuit; and
a memory map coupled to the discover circuit and storing records for a plurality of Intellectual Property blocks implemented within the integrated circuit;
wherein each Intellectual Property block is a circuit block implemented within the programmable circuitry of the integrated circuit;
wherein the discover circuit is configured to generate a list of the plurality of Intellectual Property blocks implemented within the integrated circuit from the records of the memory map responsive to the first request; and
wherein the bridge circuit is configured to send the list to the external system.

2. The integrated circuit of claim 1 , wherein:
the memory map stores security settings for the plurality of Intellectual Property blocks; and
the discover circuit generates the list by omitting selected ones of the plurality of Intellectual Property blocks from the list based on the security settings of the respective Intellectual Property blocks.

3. The integrated circuit of claim 1 , wherein:
the memory map specifies an address range for the plurality of Intellectual Property blocks; and
the discover circuit specifies the address range for the Intellectual Property blocks in the list.

4. The integrated circuit of claim 3 , wherein:
a second request is received specifying an address of an intended Intellectual Property block and having a security setting that prevents storage of a record for the intended Intellectual Property block within the memory map; and
the discover circuit compares the address with the address ranges of the memory map and selectively discards the second request according to the comparison.

5. The integrated circuit of claim 1 , wherein:
the memory map stores strings specifying Intellectual Property block configuration data for the plurality of Intellectual Property blocks implemented within the integrated circuit; and
the discover circuit includes the strings within the list.

6. The integrated circuit of claim 1 , wherein, responsive to a first Intellectual Property block implemented within the integrated circuit being replaced with a second and different Intellectual Property block, a record comprising first information for the first Intellectual Property block in the memory map is updated with second information for the second Intellectual Property block.

7. The integrated circuit of claim 6 , wherein responsive to receiving a communication comprising the second information from the second Intellectual Property block, the discover circuit updates the record of the first Intellectual Property block with the second information.

8. The integrated circuit of claim 6 , wherein
the second Intellectual Property block is implemented as part of partial reconfiguration of the integrated circuit.

9. The integrated circuit of claim 1 , wherein:
the memory map comprises a plurality of distributed memory elements implemented as part of the plurality of Intellectual Property blocks of the integrated circuit;
the distributed memory elements store the records for the plurality of Intellectual Property blocks; and
wherein the discover circuit generates the list by querying the Intellectual Property blocks for the records.

10. An integrated circuit comprising:
a processor configured to execute user program code;
programmable circuitry;
a discover circuit coupled to the processor and configured to receive a request from the processor; and
a memory map coupled to the discover circuit and storing records for a plurality of Intellectual Property blocks implemented within the integrated circuit;
wherein each Intellectual Property block is a circuit block implemented within the programmable circuitry of the integrated circuit;
wherein the discover circuit is configured to generate a list of the plurality of Intellectual Property blocks implemented within the integrated circuit from the records of the memory map responsive to the request; and
wherein the discover circuit is configured to send the list to the processor.

11. The integrated circuit of claim 10 , wherein:
the memory map stores security settings for the plurality of Intellectual Property blocks; and
the discover circuit generates the list by omitting selected ones of the plurality of Intellectual Property blocks from the list based on the security settings of the respective Intellectual Property blocks.

12. The integrated circuit of claim 10 , wherein, responsive to a first Intellectual Property block implemented within the integrated circuit being replaced with a second and different Intellectual Property block, a record comprising first information for the first Intellectual Property block in the memory map is updated with second information for the second Intellectual Property block.

13. The integrated circuit of claim 12 , wherein responsive to receiving a communication comprising the second information from the second Intellectual Property block, the discover circuit updates the record of the first Intellectual Property block with the second information.

14. The integrated circuit of claim 12 , wherein the second Intellectual Property block is implemented as part of partial reconfiguration of the integrated circuit.

15. The integrated circuit of claim 10 , wherein:
the memory map comprises a plurality of distributed memory elements implemented as part of the plurality of Intellectual Property blocks of the integrated circuit;
the distributed memory elements store the records for the plurality of Intellectual Property blocks; and
wherein the discover circuit generates the list by querying the Intellectual Property blocks for the records.

16. A method comprising:
receiving, within an integrated circuit comprising programmable circuitry, a request for information from a requesting system;
responsive to the request, reading a memory map within the integrated circuit;
wherein the memory map stores records for a plurality of Intellectual Property blocks implemented within the integrated circuit;
wherein each Intellectual Property block is a circuit block implemented within the programmable circuitry of the integrated circuit;
generating a list of the plurality of Intellectual Property blocks implemented within the integrated circuit from the memory map; and
sending the list to the requesting system.

17. The method of claim 16 , wherein the list is generated by excluding selected ones of the plurality of Intellectual Property blocks from the list based on the security settings of the respective Intellectual Property blocks.

18. The method of claim 16 , further comprising:
responsive to replacing a first Intellectual Property block of the IC with a second Intellectual Property block of the IC, updating the record of the memory map for the first Intellectual Property block with information for the second Intellectual Property block.

19. The method of claim 18 , wherein the second Intellectual Property block is implemented as part of partial reconfiguration of the integrated circuit.

20. The method of claim 16 , wherein:
the memory map comprises a plurality of distributed memory elements implemented as part of the plurality of Intellectual Property blocks of the integrated circuit;
the distributed memory elements store the rec

Assignees

• Xilinx Inc

Inventors

• Schelle Graham F
• Schumacher Paul R
• Hernandez Adrian M

Classifications

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• H03K19/17728 Primary

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2115/08

  Intellectual property [IP] blocks or IP cores · CPC title