Layout method for printed circuit board
US-9846756-B2 · Dec 19, 2017 · US
Chip packaging
Chip packaging · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F2113/18 |
| Official title | Chip packaging |
| Display label | Chip packaging |
| Total patents | 291 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 25 |
| 2016 | 27 |
| 2017 | 17 |
| 2018 | 15 |
| 2019 | 27 |
| 2020 | 37 |
| 2021 | 34 |
| 2022 | 23 |
| 2023 | 26 |
| 2024 | 24 |
| 2025 | 29 |
| 2026 | 7 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Simulation Processor with In-Package Look-Up Table
US-2017323041-A1 · Nov 9, 2017 · US
Thermal simulation device and method
US-9773080-B2 · Sep 26, 2017 · US
Methods, systems, and articles of manufacture for implementing electronic designs with a pseudo-3D analysis mechanism
US-9672319-B1 · Jun 6, 2017 · US
Thermal simulation device and method
US-2017154144-A1 · Jun 1, 2017 · US
Method for co-designing flip-chip and interposer
US-9589092-B2 · Mar 7, 2017 · US
2.5D electronic package
US-9583431-B1 · Feb 28, 2017 · US
Stacked chip layout and method of making the same
US-2017032072-A1 · Feb 2, 2017 · US
Semiconductor devices with ball strength improvement
US-2016372435-A1 · Dec 22, 2016 · US
Layout design system providing extended active area in filler design and semiconductor device fabricated using the system
US-9514260-B2 · Dec 6, 2016 · US
Interposer defect coverage metric and method to maximize the same
US-9514268-B2 · Dec 6, 2016 · US
Method of making stacked chip layout
US-9495500-B2 · Nov 15, 2016 · US
System and method for designing semiconductor package using computing system, apparatus for fabricating semiconductor package including the system, and semiconductor package designed by the method
US-9465900-B2 · Oct 11, 2016 · US
Semiconductor Device Design Methods and Conductive Bump Pattern Enhancement Methods
US-2016283639-A1 · Sep 29, 2016 · US
Methods, systems, and articles of manufacture for back annotating and visualizing parasitic models of electronic designs
US-9449130-B1 · Sep 20, 2016 · US
Semiconductor devices with ball strength improvement
US-9437567-B2 · Sep 6, 2016 · US
Integrated circuit package and method
US-9430604-B2 · Aug 30, 2016 · US
Method and apparatus for flip chip packaging co-design and co-designed flip chip package
US-2016217244-A1 · Jul 28, 2016 · US
Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance
US-2016210398-A1 · Jul 21, 2016 · US
Multi-layer circuit using metal layers as a moisture diffusion barrier for electrical performance
US-2016211229-A1 · Jul 21, 2016 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F2113/18?
- CPC G06F2113/18 is the Cooperative Patent Classification code for “Chip packaging.”
- How many patents are filed under CPC G06F2113/18 (Chip packaging)?
- Our database includes 291 publications tagged with this CPC code.
- Is patent activity under CPC G06F2113/18 growing?
- Publication counts under this code: 24 in 2024 vs 29 in 2025 (latest complete years).