Layout design system providing extended active area in filler design and semiconductor device fabricated using the system

Patent metadata

Field	Value
Publication number	US-9514260-B2
Application number	US-201414474512-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	Dec 5, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

A layout design system includes a storage unit storing first and second standard cell designs, and a displacement module that arranges the first and second standard cell designs to generate an intermediate design in accordance with the chip design requirement. A first area for the first standard cell design and a second area for the second standard cell design are separated in the intermediate design by a filler design having no active area. Extended active areas are formed in the filler design in relation to the first standard cell design and second standard cell design.

First claim

What is claimed is:

1. A layout design system that receives a chip design requirement and provides a corresponding chip design to a circuit that stores the chip design, the layout design system comprising:
a processor;
a storage unit that stores a first standard cell design defining a first active area having a first width and a second standard cell design defining a second active area having a second width different from the first width; and
a displacement module operating in conjunction with the processor and configured to;
arrange the first standard cell design in a first area and the second standard cell in a second area to generate an intermediate design in accordance with the chip design requirement, wherein the first area and the second area are separated in the intermediate design by a filler design having no active area,
generate a first marker corresponding to the first width at a first boundary between the filler design and the first area and a second marker corresponding to the second width at a second boundary between the filler design and the second area, such that the first marker and the second marker are defined in the intermediate design, and
store the intermediate design in the storage unit.

2. The layout design system of claim 1 , wherein the displacement module is further configured to measure a pitch separating the first standard cell design and the second standard cell design across the filler design, and to define a first length for the first marker and a second length for the second marker in accordance with the pitch.

3. The layout design system of claim 2 , wherein the displacement module defines each one of the first length and the second length as being ½ of the pitch.

4. The layout design system of claim 1 , further comprising:
a generation module operating in conjunction with the processor, and configured to;
receive the intermediate design from the storage unit,
modify the intermediate design by generating a first extended active area having the first width and extending the first length from the first boundary into a filler area defined by the filler design and by generating a second extended active area having the second width and extending the second length from the second boundary into the filler area to meet the first extended active area,
generate the chip design in accordance with the modified intermediate design, and
provide the chip design to the circuit storing the chip design.

5. The layout design system of claim 4 , wherein the displacement module is further configured to generate the intermediate design with a normal gate area disposed in one of the first area and the second area, and
the generation module is further configured to generate the chip design with a dummy gate area disposed in the filler area and arranged in parallel with the normal gate area.

6. The layout design system of claim 5 , wherein at least one of the displacement module and the generation module is implemented by execution of software using the processor, and the software is stored in the storage unit.

7. The layout design system of claim 4 , wherein the storage unit stores a plurality of candidate filler designs including active areas and extended active area having different shapes, and
the generation module is further configured to modify the filler design by selecting one of the plurality of candidate filler designs stored in the storage unit.

8. A layout design system that receives a chip design requirement and provides a corresponding chip design to a circuit that stores the chip design, the layout design system comprising:
a processor;
a storage unit that stores a first standard cell design defining a first active area having a first width, a second standard cell design defining a second active area having a second width different from the first width, and a filler design having no active area;
a displacement module operating in conjunction with the processor and configured to;
arrange the first standard cell design in a first area and the second standard cell in a second area to generate an intermediate design in accordance with the chip design requirement, wherein the first area and the second area are separated in the intermediate design by the filler design,
generate a first marker corresponding to the first width at a first boundary between the filler design and the first area, and a second marker corresponding to the second width at a second boundary between the filler design and the second area, such that the first marker and the second marker are defined in the intermediate design, and
store the intermediate design in the storage unit.

9. The layout design system of claim 8 , wherein the displacement module is further configured to measure a pitch separating the first standard cell design and the second standard cell design across the filler design, and to define a first length for the first marker and a second length for the second marker in accordance with the pitch.

10. The layout design system of claim 9 , wherein the displacement module defines each one of the first length and the second length as being ½ of the pitch.

11. The layout design system of claim 8 , further comprising:
a generation module operating in conjunction with the processor and configured to;
receive the intermediate design from the displacement module,
modify the intermediate design by generating a first extended active area having the first width and extending the first length from the first boundary into a filler area defined by the filler design and by generating a second extended active area having the second width and extending the second length from the second boundary into the filler area to meet the first extended active area,
generate the chip design in accordance with the modified intermediate design, and
provide the chip design to the circuit storing the chip design.

12. The layout design system of claim 11 , wherein the displacement module is further configured to generate the intermediate design with a normal gate area disposed in one of the first area and the second area, and
the generation module is further configured to generate the chip design with a dummy gate area disposed in the filler area and arranged in parallel with the normal gate area.

13. The layout design system of claim 11 , wherein the displacement module and the generation module are commonly provided by a single integrated module accessed by the processor.

14. The layout design system of claim 11 , wherein the storage unit stores a plurality of candidate filler designs including active areas and extended active area having different shapes, and
the generation module is further configured to modify the filler design by selecting one of the plurality of candidate filler designs stored in the storage unit.

15. A layout design system that receives a chip design requirement and provides a corresponding chip design to a circuit that stores the chip design, the layout design system comprising:
a processor;
a storage unit that stores a first standard cell design defining a first active area having a first width, a second standard cell design defining a second active area having a second width different from the first width, and a filler design having no active area;
a displacement module operating in conjunction with the processor and configured to;
arrange the first standard cell design in a first area and the second standard cell in a second area to generate an intermediate design in accordance with the chip design requirement, wherein the first area and the second area are separated in the interm

Assignees

• Kim Jin-Tae
• Samsung Electronics Co Ltd

Inventors

• Kim Jin-Tae

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F17/5068

  Physics · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic

• G06F2113/18

  Chip packaging · CPC title