System and method for designing semiconductor package using computing system, apparatus for fabricating semiconductor package including the system, and semiconductor package designed by the method

Patent metadata

Field	Value
Publication number	US-9465900-B2
Application number	US-201314064102-A
Country	US
Kind code	B2
Filing date	Oct 25, 2013
Priority date	Nov 15, 2012
Publication date	Oct 11, 2016
Grant date	Oct 11, 2016

Abstract

A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters.

First claim

What is claimed is:

1. A system for designing a semiconductor package, comprising:
a computing system configured to:
receive a layout parameter for a first chip, a layout parameter for a second chip that is different from the first chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts;
after generating the virtual layouts, model operating parameters for the first and second chips and the package substrate in response to the respective virtual layouts; and
analyze operating characteristics of the virtual layouts in response to the modeled operating parameters,

wherein the first and second chip are stacked on the package substrate in the plurality of virtual layouts.

2. The system for designing a semiconductor package of claim 1 , wherein:
the first chip includes a memory chip, and
the second chip includes a processor chip.

3. The system for designing a semiconductor package of claim 2 , wherein:
the memory chip includes a DRAM chip, and
the processor chip includes an AP (Application Processor) chip.

4. The system for designing a semiconductor package of claim 1 , wherein the layout parameters for the first and second chips and the layout parameter for the package substrate are provided in the form of a library.

5. The system for designing a semiconductor package of claim 4 , wherein:
the layout parameters for the first and second chips include sizes of the first and second chips, an arrangement type of pads, a number of the pads, and a pitch between the pads, and
the layout parameter for the package substrate includes a size of the package substrate, an arrangement type of package balls, a number of the package balls, and a pitch between the package balls.

6. The system for designing a semiconductor package of claim 1 , wherein connection relations among respective pads of the first chip, respective chip balls of the second chip, respective package balls of the package substrate, and respective joint balls connecting the first and second chips to the package substrate are defined by the virtual layouts.

7. The system for designing a semiconductor package of claim 1 , wherein in at least one of the virtual layouts, the second chip is arranged on the package substrate, and the first chip is arranged on the second chip.

8. The system for designing a semiconductor package of claim 1 , wherein the computing system is further configured to:
model the operating parameters for the first and second chips in response to the virtual layouts; and
model the operating parameters for the package substrate in response to the virtual layouts separate from the modelling of the operating parameters for the first and second chips.

9. The system for designing a semiconductor package of claim 1 , wherein the operating parameters of the package substrate include an S-parameter model for the package substrate.

10. The system for designing a semiconductor package of claim 1 , wherein the operating parameters include a signal parameter and a power parameter.

11. The system for designing a semiconductor package of claim 10 , wherein the computing system is further configured to model the signal parameter of the package substrate on the basis of a length of a signal path of the package substrate based on the virtual layouts.

12. The system for designing a semiconductor package of claim 1 , wherein the operating characteristics of the virtual layouts include signal integrity, power integrity, and temperature integrity of the generated virtual layouts.

13. The system for designing a semiconductor package of claim 1 , wherein the computing system is further configured to select any one of the virtual layouts in response to the operating characteristics.

14. The system for designing a semiconductor package of claim 1 , wherein the first chip includes two chips.

15. The system for designing a semiconductor package of claim 1 , wherein the computing system is further configured to receive a layout parameter for another substrate and generate the virtual layouts in response to the layout parameter of the other substrate.

16. A computing system comprising:
a storage storing therein a program for designing a layout of a semiconductor package, which includes a first chip, a second chip that is different from the first chip, and a package substrate; and
a processor coupled to the storage and configured to operate in response to the program;
wherein the program includes:
a virtual stacking module configured to receive a layout parameter for the first chip, a layout parameter for the second chip, and a layout parameter for the package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate virtual layouts;
a modeling module configured to, after the generation of the virtual layouts, model operating parameters for the first and second chips and the package substrate in response to the respective virtual layouts;
a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters; and
a reviewing module configured to select any one of the plurality of generated virtual layouts in response to the analyzed operating characteristics,

wherein the first and second chip configured to stack on the package substrate based on the virtual layouts.

17. The computing system of claim 16 , wherein
the virtual stacking module is configured to receive the layout parameter for the first chip in a first chip library,
the virtual stacking module is configured to receive the layout parameter for the second chip in a second chip library,
the virtual stacking module is configured to receive the layout parameter for the package substrate in a package substrate library, and
the first and second chip libraries and the package substrate library are stored in the storage.

18. The computing system of claim 16 , further comprising a main memory configured to load the virtual stacking module, the modeling module, the characteristic analyzing module, and the reviewing module so that the central processing unit can perform procedures included in the virtual stacking module, the modeling module, the characteristic analyzing module, and the reviewing module.

19. A semiconductor package comprising:
a package substrate;
a first chip mounted on the package substrate according to a layout; and
a second chip which is mounted on the package substrate according to the layout and is different from the first chip,
wherein the layout is determined by:
receiving a layout parameter for the first chip, a layout parameter for the second chip that is different from the first chip, and a layout parameter for the package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generating a plurality of virtual layouts;
after generating the virtual layouts, modeling a plurality of operating parameters for the first and second chips and the package substrate in response to the respective virtual layouts;
analyzing operating characteristics of the respective virtual layouts in response to the respective modeled operating parameters; and
selecting any one of the virtual layouts in response to the analyzed operating characteristics,
wherein the first and second chip configured to stack on the package substrate based on the plurality of virtu

Assignees

• Jeong Jae-Hoon
• Lee Won-Cheol
• Cheon Young-Hoe
• Hwang Bo-Sun
• Hwang Chan-Seok
• Samsung Electronics Co Ltd

Inventors

• Jeong Jae-Hoon
• Lee Won-Cheol
• Cheon Young-Hoe
• Hwang Bo-Sun
• Hwang Chan-Seok

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title