Integrated circuit package and method

Patent metadata

Field	Value
Publication number	US-9430604-B2
Application number	US-201414250168-A
Country	US
Kind code	B2
Filing date	Apr 10, 2014
Priority date	Dec 18, 2013
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Various example embodiments are directed to methods and apparatuses for implementing a circuit design within an integrated circuit (IC) package. A respective capacitance is determined for each die contact of a circuit design. A respective target inductance range is selected for each of the plurality of die contacts based on the determined capacitance. A segmentation of the circuit design is determined as a function of the target inductance ranges. The segmentation defines an implementation of the circuit design on a plurality of IC dies. The IC dies are placed at respective locations on the substrate, based on the resulting inductances of connections (e.g., conductive traces) between the die contacts and terminals of the IC package.

First claim

What is claimed is:

1. A method for implementing a circuit design within an integrated circuit (IC) package having substrate and terminals for carrying signals communicated by the circuits of the circuit design, the method comprising:
determining a respective capacitance of each die contact of a plurality of die contacts of a circuit design;
selecting a respective target inductance range for each of the plurality of die contacts based on the determined capacitance of the die contact;
determining as a function of the target inductance ranges, a segmentation of the circuit design that defines at least a first IC die and a second IC die; and
placing the first and second IC dies at respective locations on the substrate, at which the inductance of each connection, from the plurality of die contacts to terminals of the IC package, is within the target inductance range of the corresponding die contact;
wherein determining the segmentation of the circuit design that defines at least a first IC die and a second IC die includes:
assigning an initial segmentation of the circuit design defining the first IC die and the second IC die;
assigning an initial first location for the first IC die on the substrate and an initial second location for the second IC die on the substrate;
for each connection from one of the plurality of the die contacts of the circuit design to a respective terminal of the IC package, calculating a characteristic inductance for the connection; and
wherein placing the first and second IC dies at respective locations on the substrate includes, in response to the calculated characteristic inductance falling outside the target inductance range, laterally displacing at least one of the first and second IC dies on the substrate as a function of the calculated characteristic inductance.

2. The method of claim 1 , wherein the selecting of the target inductance range for each die contact includes, for each die contact of the plurality of die contacts, selecting the respective target inductance range based on the determined capacitance and a respective frequency response parameter.

3. The method of claim 2 , wherein the determining of the respective capacitance of each die contact of the plurality of die contacts includes simulating the circuit design.

4. The method of claim 2 , further comprising:
simulating the circuit design to determine a respective highest frequency of signals carried by each of the plurality of die contacts; and
for each of the plurality of die contacts, determining the respective frequency response parameter based on the respective highest frequency.

5. The method of claim 2 , further comprising: retrieving the frequency response parameter for each of the plurality of die contacts from a package model specification.

6. The method of claim 1 , wherein the connections between the plurality of die contacts and the terminals of the IC package are conductive traces on the substrate.

7. The method of claim 1 , further comprising: routing each connection, from the plurality of die contacts to terminals of the IC package, to have a length causing the connection to have an inductance within the target inductance range of the corresponding die contact.

8. The method of claim 1 , wherein the selecting of the target inductance range for each die contact includes, for each die contact of the plurality of die contacts, selecting the respective target inductance range based on the determined capacitance and a respective delay or skew parameter.

9. The method of claim 1 , wherein selecting the respective target inductance range includes selecting the target inductance range.

10. The method of claim 1 , wherein determining the segmentation of the circuit design includes providing a conductive trace having an increased length that provides a higher inductance and capacitance.

11. The method of claim 1 ,
wherein said terminals are configured and arranged to carry high-bandwidth signals;
further including a plurality of second terminals configured and arranged to carry low-bandwidth signals.

12. The method of claim 11 , wherein selecting the target inductance range includes, for each of the die contacts, selecting a target inductance range based on the determined capacitance and a frequency response parameter.

13. The method of claim 12 , further comprising:
simulating the circuit design to determine a respective highest frequency of signals carried by each of the plurality of die contacts; and
for each of the plurality of die contacts, determining the frequency response parameter for the die contact based on the determined highest frequency of signals carried by the die contact.

14. The method of claim 11 , further including, in response to the calculated characteristic inductance falling outside the target inductance range, recalculating the characteristic inductance for each connection and repeating the step of laterally displacing until either of the following conditions is detected:
(i) the characteristic inductances are within the target inductance ranges, or
(ii) the target inductance ranges cannot be met using the initial segmentation.

15. The method of claim 14 , further comprising, in response to determining that the target inductance ranges are not met using said segmentation, assigning a second segmentation of the circuit design that is different from said segmentation.

16. The method of claim 14 , further comprising, in response to determining that the target inductance ranges are not met using said segmentation, assigning a second segmentation of the circuit design that is different than the initial segmentation, and repeating the steps of assigning the initial first location and calculating a characteristic inductance with the second segmentation of the circuit design.

17. The method of claim 11 , wherein calculating the characteristic inductance for the connection includes calculating a characteristic inductance for a connection from one of the plurality of the die contacts to a respective terminal of the IC package, based on a shortest length connection between the one of the plurality of die contacts and the respective terminal.

18. The method of claim 11 , further comprising routing each connection, from the plurality of die contacts to terminals of the IC package, to have a length causing the connection to have an inductance within the target inductance range of the corresponding die contact.

Assignees

• Nxp Bv

Inventors

• Kim Jong
• Spehar James
• Zhang Xu

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W44/00

  Electrical arrangements for controlling or matching impedance · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F2113/18

  Chip packaging · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title