Thermal simulation device and method

Patent metadata

Field	Value
Publication number	US-9773080-B2
Application number	US-201514985204-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	Nov 30, 2015
Publication date	Sep 26, 2017
Grant date	Sep 26, 2017

Abstract

A thermal simulation device is applied to a transaction-level designed chip which includes a plurality of intellectual properties. The thermal simulation device includes a plurality of thermal-aware transaction-level power model circuits, a simulator, a translator and a thermal emulator. The thermal-aware transaction-level power model circuits corresponds to the respective intellectual properties, and are configured to a corresponding power information for each of the intellectual properties, and dynamically adjusts the power information according to temperature information. The simulator is configured to generate the corresponding temperature information of the intellectual properties according to compatible information. The translator is configured to generate the compatible information which is compatible with the simulator. The thermal emulator is configured to trigger the simulator and transmit the temperature information to the intellectual properties.

First claim

What is claimed is:

1. A thermal simulation device, applied to a transaction-level designed chip, wherein the chip includes a plurality of intellectual properties, the thermal simulation device comprising:
a plurality of thermal-aware transaction-level power model circuits applied for thermal simulation of the chip, corresponding to the plurality of intellectual properties, and configured to generate power information corresponding to the plurality of intellectual properties, and dynamically adjust the power information according to temperature information;
a simulator, configured to generate the temperature information corresponding to the plurality of intellectual properties according to compatible information;
a translator, configured to generate the compatible information which is compatible with the simulator; and
a thermal emulator, configured to trigger the simulator and transmit the temperature information to the intellectual properties,
wherein each of the intellectual properties is divided into a plurality of grids in advance, wherein each of the grids corresponds to the same or different power weighting,
wherein when each of the intellectual properties is divided into the plurality of grids in advance, a first maximum temperature difference corresponding to the first number of grids of each of the intellectual properties is computed and a second maximum temperature difference corresponding to the second number of grids of each of the intellectual properties is computed, and a first difference between the first maximum temperature difference and the second maximum temperature difference is computed, wherein the second number is larger than the first number,
wherein when the first difference is less than or equal to a threshold, the first number is adopted; and when the first difference is greater than the threshold, a third maximum temperature difference corresponding to the third number of grids of each of the intellectual properties is computed; and a second difference between the second maximum temperature difference and the third maximum temperature difference is computed, and a determination is made as to whether the second difference is greater than the threshold, wherein the third number is larger than the second number.

2. The thermal simulation device of claim 1 , wherein the thermal-aware transaction-level power model circuit further comprises a thermal code, and the thermal-aware transaction-level power model circuit further generates the power information according to the temperature information through the thermal code.

3. The thermal simulation device of claim 1 , wherein each of the thermal-aware transaction-level power model circuits is further configured to adopt a coarse or a fine-grid design method by determining whether each of the intellectual properties is divided into multiple grids.

4. The thermal simulation device of claim 1 , wherein each of the thermal-aware transaction-level power model circuits further comprises a look-up table and the look-up table is established according to the relationship between temperature and power of each thermal-aware transaction-level power model circuit.

5. The thermal simulation device of claim 4 , wherein each of the thermal-aware transaction-level power model circuits obtains the power information according to the look-up table.

6. The thermal simulation device of claim 1 , wherein the simulator is a PSPICE Simulation Engine, a HSPICE Simulation Engine, a Spectra Simulation Engine, or a Nexxim SPICE Simulation Engine.

7. The thermal simulation device of claim 1 , wherein the translator generates a resistor-capacitor network of each of the intellectual properties according to floorplan and material of each of the intellectual properties and generates parameter information corresponding to the resistor-capacitor network according to the resistor-capacitor network.

8. The thermal simulation device of claim 7 , wherein the translator is further configured to transform the power information to current information, and wherein the compatible information comprises the parameter information and the current information.

9. The thermal simulation device of claim 1 , further comprising:
a decision circuit, configured to determine the chip is a 2 dimension chip or a 3 dimension chip.

10. The thermal simulation device of claim 9 , wherein when the chip is the 2 dimension chip, a numerical method or an analytical method is performed.

11. The thermal simulation device of claim 9 , wherein the thermal simulation device is applied to different designed models for different time-levels, wherein the design models are Cycle Accurate (CA), Programmer View with Timing (PVT), Programmer View (PV), and untimed.

12. The thermal simulation device of claim 1 , wherein the temperature information transmitted to the intellectual properties is implemented in the chip for manufacturing the chip.

13. A thermal simulation method, applied to a transaction-level designed chip, wherein the chip includes a plurality of intellectual properties, the thermal simulation method comprising:
generating, by a plurality of thermal-aware transaction-level power model circuits applied for thermal simulation of the chip, power information corresponding to the plurality of intellectual properties;
generating compatible information which is compatible with a simulator;
generating temperature information corresponding to the plurality of intellectual properties according to the compatible information;
transmitting the temperature information to the intellectual properties; and
dynamically adjusting the power information according to the temperature information,
wherein each of the intellectual properties is divided into a plurality of grids in advance, wherein each of the grids corresponds to the same or different power weighting,
wherein when each of the intellectual properties is divided into the plurality of grids in advance, the thermal simulation method further comprising:
computing a first maximum temperature difference corresponding to the first number of grids of each of the intellectual properties and computing a second maximum temperature difference corresponding to the second number of grids of each of the intellectual properties, wherein the second number is larger than the first number;
computing a first difference between the first maximum temperature difference and the second maximum temperature difference;
determining whether the first difference is larger than a threshold;
adopting the first number when the first difference is less than or equal to a threshold;
computing a third maximum temperature difference corresponding to the third number of grids of each of the intellectual properties when the first difference is greater than the threshold, wherein the third number is larger than the second number;
computing a second difference between the second maximum temperature difference and the third maximum temperature difference; and
determining whether the second difference is greater than the threshold.

14. The thermal simulation method of claim 13 , further comprising:
generating, by the thermal-aware transaction-level power model circuit, the power information according to the temperature information through a thermal code.

15. The thermal simulation method of claim 13 , further comprising:
adopting a coarse or a fine-grid design method by determining whether each of the intellectual properties is divided into multiple grids.

16. The thermal simulation method of claim 13 , wherein each of the thermal-aware transaction-level power model c

Assignees

• Ind Tech Res Inst

Inventors

• Chang Yeong-Jar
• Lu Juin-Ming
• Cheng Liang-Chia

Classifications

• G06F30/331

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F2113/18

  Chip packaging · CPC title

• G06F30/20 Primary

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F2115/06

  Structured ASICs · CPC title