Layout method for printed circuit board

Patent metadata

Field	Value
Publication number	US-9846756-B2
Application number	US-201514843113-A
Country	US
Kind code	B2
Filing date	Sep 2, 2015
Priority date	Oct 12, 2012
Publication date	Dec 19, 2017
Grant date	Dec 19, 2017

Abstract

A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

First claim

What is claimed is:

1. A layout method for a printed circuit board (PCB), comprising:
obtaining a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB;
obtaining a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules;
obtaining a plurality of PCB parameters;
selecting a specific routing module from the module group according to the PCB parameters;
implementing the specific routing module into a layout design for PCB fabrication,
wherein the specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip;
generating a PCB layout based at least on the layout information and the routing configuration; and
generating at least one physical mask based at least in part on the PCB layout for use in PCB fabrication.

2. The layout method as claimed in claim 1 , wherein the DRAM is a mobile memory, and the DRAM and a flash memory are packaged in the memory chip.

3. The layout method as claimed in claim 1 , wherein the main chip is a system on chip (SOC) chip.

4. The layout method as claimed in claim 1 , wherein the step of obtaining the module group from the database according to the memory type of the DRAM further comprises:
transmitting a requirement corresponding to the memory type of the DRAM, to the database; and
receiving the routing modules corresponding to the memory type of the DRAM from the database,
wherein the database is disposed in a server, and the server provides the routing modules in response to the requirement.

5. The layout method as claimed in claim 4 , wherein the requirement comprises information regarding a PCB electronic design automation (EDA) tool.

6. The layout method as claimed in claim 1 , wherein the PCB parameters comprises a layer count, a stack-up setting, a via type and component placement information of the PCB.

7. The layout method as claimed in claim 6 , wherein the via type of the PCB represents whether a plurality of vias of the PCB are stagger vias or stacked vias.

8. The layout method as claimed in claim 6 , wherein the component placement information represents whether the PCB is a single-sided PCB or a double-sided PCB.

9. The layout method as claimed in claim 1 , wherein the step of implementing the specific routing module into the layout design of the PCB further comprises:
fully implementing the specific routing module into the layout design of the PCB, so as to completely implement the main chip, the memory chip and the routing configuration into the layout design of the PCB; or
partially implementing the specific routing module into the layout design of the PCB, so as to completely implement the main chip and the memory chip and partially implement the routing configuration into the layout design of the PCB.

10. A layout method for a printed circuit board (PCB), comprising:
obtaining electronic design automation (EDA) information regarding a PCB EDA tool;
obtaining a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB;
obtaining a module group from a database according to the memory type of the DRAM and the EDA information, wherein the module group comprises a plurality of routing modules;
obtaining a plurality of PCB parameters;
selecting a specific routing module from the module group according to the PCB parameters;
implementing the specific routing module into a layout design for PCB fabrication provided by the PCB EDA tool,
wherein the specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip;
generating a PCB layout based at least on the layout information and the routing configuration; and
generating at least one physical mask based at least in part on the PCB layout for use in PCB fabrication.

11. The layout method as claimed in claim 10 , wherein the DRAM is a mobile memory, and the DRAM and a flash memory are packaged in the memory chip.

12. The layout method as claimed in claim 10 , wherein the main chip is a system on chip (SOC) chip.

13. The layout method as claimed in claim 10 , wherein the step of obtaining the module group from the database according to the memory type of the DRAM and the EDA information further comprises:
transmitting a requirement corresponding to the memory type of the DRAM and the EDA information, to the database; and
receiving the routing modules corresponding to the memory type of the DRAM from the database,
wherein the database is disposed in a server, and the server provides the routing modules in response to the requirement.

14. The layout method as claimed in claim 10 , wherein the PCB parameters comprises a layer count, a stack-up setting, a via type and component placement information of the PCB.

15. The layout method as claimed in claim 14 , wherein the via type of the PCB represents whether a plurality of vias of the PCB are stagger vias or stacked vias.

16. The layout method as claimed in claim 14 , wherein the component placement information represents whether the PCB is a single-sided PCB or a double-sided PCB.

17. The layout method as claimed in claim 10 , wherein the step of implementing the specific routing module into the layout design of the PCB further comprises:
fully implementing the specific routing module into the layout design of the PCB, so as to completely implement the main chip, the memory chip and the routing configuration into the layout design of the PCB; or
partially implementing the specific routing module into the layout design of the PCB, so as to completely implement the main chip and the memory chip and partially implement the routing configuration into the layout design of the PCB.

18. A layout method for a printed circuit board (PCB), comprising:
obtaining a project ID corresponding to the PCB from a client;
recognizing the project ID to determine whether the project ID exists in an account list;
obtaining at least one module group from a database of a server according to the project ID when the project ID does not exist in the account list, wherein the module group comprises a plurality of routing modules;
obtaining a plurality of PCB parameters;
selecting at least one specific routing module from the module group according to the PCB parameters;
providing the specific routing module to the client and adding the project ID into the account list,
wherein the specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip,
wherein the client implements the specific routing module into a layout design for PCB fabrication;
generating a PCB layout based at least on the layout information and the routing configuration; and
generating at least one physical mask based at least in part on the PCB layout for use in PCB fabrication.

19. The layout method as claimed in claim 18 , wherein the DRAM is a mobile memory, and the DRAM and a flash memory are packaged in the memory chip.

20. The layout method as claimed in claim 18 , wherein the main chip is a system on chip (SOC) chip.

21. The layout method as claimed in claim 18 , further comprising:
obtaining PCB information regarding a PCB electronic design automation (EDA) tool,
wherein the module group is obtained according to the project ID and the PCB information.

Assignees

• Mediatek Inc

Inventors

• Pan Fu-Kang
• Chen Nan-Cheng
• Lin Shih-Chieh
• Tang Hui-Chi
• Liu Ying
• Liu Yang
• Li Ching-Chih

Classifications

• G06F2113/20

  Packaging, e.g. boxes or containers · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F2113/18

  Chip packaging · CPC title

• G06F17/5072 Primary

  Physics · mapped topic