Distributing timing over Metro Transport Networking
US-2020412471-A1 · Dec 31, 2020 · US
at clock signal level
at clock signal level · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F11/1679 |
| Official title | {at clock signal level} |
| Display label | at clock signal level |
| Total patents | 114 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly declining.
| Year | Patents |
|---|---|
| 2015 | 8 |
| 2016 | 11 |
| 2017 | 12 |
| 2018 | 15 |
| 2019 | 5 |
| 2020 | 15 |
| 2021 | 8 |
| 2022 | 10 |
| 2023 | 13 |
| 2024 | 12 |
| 2025 | 3 |
| 2026 | 2 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Semiconductor device and method of operating the same
US-2020394147-A1 · Dec 17, 2020 · US
Fault tolerant clock monitor system
US-10795783-B2 · Oct 6, 2020 · US
Integrated Circuit Chip with Cores Asymmetrically Oriented With Respect To Each Other
US-2020233758-A1 · Jul 23, 2020 · US
Method, clock recovery module as well as computer program for recovering a clock signal from a data signal
US-2020167246-A1 · May 28, 2020 · US
Techniques for duty cycle correction
US-2020119721-A1 · Apr 16, 2020 · US
Mram noise mitigation for background operations by delaying verify timing
US-2020057687-A1 · Feb 20, 2020 · US
Memory error detection
US-10558520-B2 · Feb 11, 2020 · US
Diverse redundant processing modules for error detection
US-2020019477-A1 · Jan 16, 2020 · US
Error detection using vector processing circuitry
US-2019340054-A1 · Nov 7, 2019 · US
Techniques For Determining Timestamp Inaccuracies In A Transceiver
US-2019319729-A1 · Oct 17, 2019 · US
Processor system and fault detection method thereof
US-10430301-B2 · Oct 1, 2019 · US
Fault Tolerant Clock Monitor System
US-2019114235-A1 · Apr 18, 2019 · US
Method and apparatus for enabling temporal alignment of debug information
US-10169171-B2 · Jan 1, 2019 · US
Process synchronization control system and process synchronization control method
US-10165314-B2 · Dec 25, 2018 · US
Loosely-coupled lock-step chaining
US-2018349214-A1 · Dec 6, 2018 · US
Method and device for recognizing hardware errors in microprocessors
US-2018336107-A1 · Nov 22, 2018 · US
Data mirror invalid timestamped write handling
US-10101941-B2 · Oct 16, 2018 · US
BIOS real-time clock update
US-10101765-B2 · Oct 16, 2018 · US
Multiplex system
US-2018293142-A1 · Oct 11, 2018 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F11/1679?
- CPC G06F11/1679 is the Cooperative Patent Classification code for “at clock signal level.”
- How many patents are filed under CPC G06F11/1679 (at clock signal level)?
- Our database includes 114 publications tagged with this CPC code.
- Is patent activity under CPC G06F11/1679 growing?
- Publication counts under this code: 12 in 2024 vs 3 in 2025 (latest complete years).