Processor system and fault detection method thereof

Patent metadata

Field	Value
Publication number	US-10430301-B2
Application number	US-201715432588-A
Country	US
Kind code	B2
Filing date	Feb 14, 2017
Priority date	Mar 14, 2016
Publication date	Oct 1, 2019
Grant date	Oct 1, 2019

Abstract

Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.

First claim

What is claimed is:

1. A processor system comprising:
a first processor configured to generate a first output signal;
a second processor configured to perform an identical task to the first processor, and configured to generate a second output signal; and
a defect detector configured to compare the first output signal with the second output signal to generate a fault detection signal,
wherein the defect detector comprises:
a first FIFO buffer configured to receive the first output signal in synchronization with a first driving voltage and a first driving clock, and store the received first output signal;
a second FIFO buffer configured to receive the second output signal in synchronization with a second driving voltage and a second driving clock, and store the received second output signal;
a level shifter configured to shift, to a level of the first driving voltage, an output from the second FIFO buffer in synchronization with the second driving clock; and
an actuator interface configured to provide an actuator driving signal to an actuator; and
wherein the defect detector is configured to perform level synchronization or clock domain synchronization on the first output signal and the second output signal.

2. The processor system of claim 1 , wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.

3. The processor system of claim 1 , wherein the first and second driving clocks are respectively provided from different phase locked loops (PLLs) or different delay locked loops (DLLs).

4. The processor system of claim 1 , wherein, when the first and second output signals are determined to be identical, the defect detector outputs any one of the first and second output signals as the actuator driving signal.

5. The processor system of claim 4 , wherein, when the first and second output signals are determined not to be identical, the defect detector outputs the fault detection signal.

6. The processor system of claim 1 , wherein the defect detector comprises a clock domain signal deliverer configured to convert an output of the level shifter to a clock domain of the first driving clock.

7. The processor system of claim 6 , wherein the defect detector comprises a comparator configured to compare an output from the first FIFO buffer and an output from the clock domain signal deliverer.

8. The processor system of claim 7 , wherein the comparator compares the output from the first FIFO buffer and the output from the clock domain signal deliverer using the first driving clock and the first driving voltage.

9. The processor system of claim 1 , further comprising:
an automotive electronic system configured to drive the actuator with reference to a result of comparing the first and second output signals.

10. A fault detecting method for a processor system, which comprises a plurality of processors, the method comprising:
receiving a first output signal from a first processor driven by a first driving voltage and a first driving clock;
receiving a second output signal from a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor;
level-synchronizing the second output signal by converting a voltage level of the second output signal to a voltage level identical to a voltage level of the first driving voltage;
clock-synchronizing the second output signal by converting a clock domain of the level-synchronized second output signal to be identical to a clock domain of the first driving clock; and
comparing the second output signal with the first output signal to generate a fault detection signal.

11. The fault detecting method of claim 10 , further comprising:
generating the fault detection signal when the first output signal and the level-synchronized and clock-synchronized second output signal are different from each other.

12. The fault detecting method of claim 10 , wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Kwon Young-Su
• Byun Kyung Jin
• Eum Nak Woong

Classifications

• G06F11/1679

  at clock signal level · CPC title

• G06F11/1608 Primary

  Error detection by comparing the output signals of redundant hardware (G06F11/1629, G06F11/1666 take precedence; error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18; checking static stores for correct operation G11C29/00; for logic circuits H03K19/003, H03K19/007; for pulse counters or frequency dividers H03K21/40) · CPC title

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G06F11/1675

  Temporal synchronisation or re-synchronisation of redundant processing components · CPC title