US2018293142A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018293142-A1 |
| Application number | US-201515766323-A |
| Country | US |
| Kind code | A1 |
| Filing date | Dec 3, 2015 |
| Priority date | Dec 3, 2015 |
| Publication date | Oct 11, 2018 |
| Grant date | — |
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Each of a plurality of input units (110) outputs an input notification (104) at the input timing at which input data (101) is input and outputs input data at the synchronization timing which is the timing of the later one of the input timing and a timing at which an input notification is output from another input unit. Each of a plurality of computing units (120) starts a computation when input data output from an associated input unit is input.
Opening claim text (preview).
1 - 11 . (canceled) 12 . A multiplex system comprising a plurality of input circuits to which data is input respectively, wherein each of the plurality of input circuits outputs an input notification at an input timing at which the data is input, and when a synchronization timing is reached by a limit timing, outputs the data at the synchronization timing, and when the synchronization timing is not reached by the limit timing, outputs the data at the limit timing, the synchronization timing being a timing of a later one of the input timing and a timing at which an input notification is output from another input circuit. 13 . The multiplex system according to claim 12 , wherein the limit timing is a timing at which a time elapsed since previous input data is output reaches an allowed time. 14 . The multiplex system according to claim 13 , wherein each of the plurality of input circuits includes: a storage circuit to which data is input and in which the data is stored; a notification circuit to detect a timing at which the data is stored in the storage circuit as the input timing and to output an input notification; a detection circuit which is an element to detect the timing of the later one of the input timing and the timing at which the input notification is output from the other input circuit as the synchronization timing, and an element to detect a preceding timing which is a timing of a faster one of the synchronization timing and the limit timing; and a synchronization circuit to read the data from the storage circuit and to output the data when the preceding timing is detected.
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