Error detection using vector processing circuitry

Patent metadata

Field	Value
Publication number	US-2019340054-A1
Application number	US-201716475487-A
Country	US
Kind code	A1
Filing date	Dec 12, 2017
Priority date	Jan 24, 2017
Publication date	Nov 7, 2019
Grant date	—

Abstract

A data processing apparatus (2) has scalar processing circuitry (32-42) and vector processing circuitry (38, 40, 42). When executing main scalar processing on the scalar processing circuitry (32-42), or main vector processing using a subset of said plurality of lanes on the vector processing circuitry (38, 40, 42), checker processing is executed using at least one lane of the plurality of lanes on the vector processing circuitry (38, 40, 42), the checker processing comprising operations corresponding to at least part of the main scalar/vector processing. Errors can then be detected based on a comparison of an outcome of the main processing and an outcome of the checker processing. This provides a technique for achieving functional safety in a high end processor with better performance and reduced hardware cost compared to a dual/triple core lockstep approach.

First claim

1 . An error detection method for a data processing apparatus comprising scalar processing circuitry to perform scalar processing of scalar operands and vector processing circuitry to perform vector processing comprising a plurality of lanes of processing performed on vector operands comprising a plurality of data elements;
the method comprising: executing main processing comprising at least one of: main scalar processing on the scalar processing circuitry, and main vector processing using a subset of said plurality of lanes on the vector processing circuitry; executing checker processing using at least one lane of said plurality of lanes on the vector processing circuitry, the checker processing comprising operations corresponding to at least part of the main processing; and performing error detection in dependence on a comparison of an outcome of said at least part of the main processing and an outcome of the checker processing.

2 . The method of claim 1 , wherein the checker processing is executed on a different hardware functional unit to the main processing.

3 . The method of any of claim 1 , wherein the comparison of the outcome of said at least part of the main processing and the outcome of the checker processing is performed on performing a store operation for storing data resulting from the main processing to a data store.

4 . The method of claim 3 , wherein the comparison of the outcome of said at least part of the main processing and the outcome of the checker processing is performed in response to a store instruction for controlling the data processing apparatus to perform said store operation for storing data resulting from the main processing to the data store.

5 . The method of claim 1 , wherein operands or status information for the main processing are stored in a different part of hardware register storage to operands or status information for the checker processing.

6 . The method of claim 1 , wherein on performing a load operation of the main scalar processing for loading data from a data store to a scalar register file, or a load operation of the main vector processing for loading data from the data store to a part of a vector register file corresponding to said subset of said plurality of lanes, the loaded data is also loaded to a part of the vector register file corresponding to said at least one lane used for the checker processing.

7 . The method of claim 6 , wherein the loading of data to said part of the vector register file corresponding to said at least one lane is performed in response to an instruction for controlling the load operation of the main scalar processing or the load operation of the main vector processing.

8 . The method according to claim 1 , wherein at least one vector register of a vector register file is reserved for use by said checker processing.

9 . The method according to claim 1 , wherein said plurality of lanes comprise at least one checker lane reserved for the checker processing.

10 . The method according to claim 9 , wherein said at least one checker lane includes a scalar checker lane reserved for performing the checker processing when the main processing comprises the main scalar processing.

11 . The method according to claim 10 , wherein instructions for controlling the vector processing circuitry to perform the checker processing corresponding to the main scalar processing are associated with predicate information for controlling the vector processing circuitry to mask an outcome of said plurality of lanes other than said scalar checker lane.

12 . The method according to claim 10 , wherein instructions for controlling the vector processing circuitry to perform at least one of the main vector processing and the checker processing corresponding to the main vector processing are associated with predicate information for controlling the vector processing circuitry to mask an outcome of said scalar checker lane.

13 . The method according to claim 1 , comprising decoding a sequence of instructions including instructions for controlling the data processing apparatus to perform the main processing, the checker processing and the error detection.

14 . The method according to claim 13 , wherein at least one instruction of the sequence instructions specifies annotation information indicating that the checker processing is to be performed on a different hardware functional unit to the main processing.

15 . The method according to claim 1 , wherein the data processing apparatus comprises an instruction decoder for decoding instructions;
wherein in response to a scalar-vector comparison instruction, when the main processing comprises said main scalar processing, the instruction decoder controls the data processing apparatus to perform said comparison of the outcome of said at least part of the main processing and the outcome of the checker processing.

16 . The method according to claim 15 , wherein the scalar-vector comparison instruction specifies a given scalar register, and said comparison comprises a comparison of a value in the given scalar register with a value in a data element of a vector register used by the checker processing.

17 . The method according to claim 15 , wherein said comparison comprises a comparison of one or more scalar status flags set in response to the main scalar processing with one or more vector status flags set in response to the checker processing.

18 . The method according to claim 15 , wherein the instruction decoder is responsive to the scalar-vector comparison instruction to control the data processing apparatus to conditionally branch to a target instruction address in dependence on the outcome of said comparison.

19 . The method according to claim 1 , wherein the data processing apparatus has a plurality of modes of operation including:
a first mode in which the checker processing is executed in addition to said main processing; and a second mode in which execution of the checker processing is suppressed.

20 . The method according to claim 19 , wherein the number of lanes of vector processing available for use in the main vector processing in the first mode is less than the number of lanes of vector processing available for use in vector processing performed in the second mode.

21 . The method according to claim 1 , wherein the data processing apparatus comprises an instruction decoder to map a first sequence of instructions comprising instructions defining the main processing to a second sequence of instructions comprising instructions defining the main processing and the checker processing, and to control the data processing apparatus to perform data processing based on the second sequence of instructions.

22 . The method according to claim 21 , wherein the second sequence of instructions also comprises instructions for controlling the data processing apparatus to perform said comparison of the outcome of said at least part of the main processing and the outcome of the checker processing.

23 . The method according to claim 21 , wherein the instruction decoder is configured to map a scalar instruction of the first sequence of instructions to a scalar instruction and a checker vector instruction of the second sequence of instructions.

24 . The method according to claim 21 , wherein in response to a scalar instruction of the first sequence of instructions corresponding to an operation unsupported by the vector processing circuitry i

Assignees

• Advanced Risc Mach Ltd

Inventors

• Boettcher Matthias Lothar
• Eyole Mbou
• Premillieu Nathanael

Classifications

• G06F9/3889

  controlled by multiple instructions, e.g. MIMD, decoupled access or execute · CPC title

• G06F8/41

  Compilation · CPC title

• G06F11/1683

  at instruction level · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F11/1637 Primary

  using additional compare functionality in one or some but not all of the redundant processing components · CPC title