Memory error detection

Patent metadata

Field	Value
Publication number	US-10558520-B2
Application number	US-201715838161-A
Country	US
Kind code	B2
Filing date	Dec 11, 2017
Priority date	May 18, 2006
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

First claim

We claim:

1. A dynamic random access memory (DRAM) device, comprising:
a memory array;
an interface to receive an address and data associated with a write operation to the memory array;
a buffer to store the address for a configurable period of time;
circuitry to perform the write operation if, within the configurable period of time, a determination is made that the address does not contain an error; and
a transmitter to transmit, to a memory controller, error information associated with the address.

2. The DRAM device of claim 1 , wherein, within the configurable period of time, in response to an indication that the address contains an error, the circuitry is to discard the data without writing the data into the memory array.

3. The DRAM device of claim 1 , wherein the memory device includes circuitry to compute a cyclic redundancy code (CRC) based on the data, the CRC to be used to determine whether there is error in the data.

4. The DRAM device of claim 1 , wherein the transmitter further transmits error information associated with the data to the memory controller.

5. The DRAM device of claim 4 , wherein the error information associated with the data transmitted by the DRAM device to the memory controller is alone sufficient for the memory controller to differentiate an error in the address, from an error in the data.

6. The DRAM device of claim 4 , wherein the interface is to receive a command to retry the write operation to overwrite erroneous data which was written into the memory array at the address if the information represents error in the associated data.

7. The DRAM device of claim 1 , wherein the circuitry is to queue a number memory operations, including the write command and including a read command received after the write command.

8. The DRAM device of claim 1 , wherein the DRAM device is programmable so as to configure the buffer according to the configurable period of time.

9. The DRAM device of claim 1 , wherein the DRAM device further comprises circuitry to calibrate the configurable period of time during a start-up sequence, and to responsively configure the buffer according to the configurable period of time.

10. The DRAM device of claim 1 , wherein a determination that an error exists in the address is made by the memory controller, wherein the DRAM device is to receive from the memory controller an indication in the form of an abort command responsive to the determination that the error exists, wherein the circuitry is to write the data into the memory array at the address in absence of the DRAM device receiving the abort command within the configurable period of time and, wherein further, the buffer is configured such that the configurable period of time is longer than a time required to transmit the error information to the memory controller, a time to make the determination, and a time for the memory controller to responsively transmit the abort command to the DRAM device.

11. A method of operating a dynamic random access memory (DRAM) device, the method comprising:
receiving an address and data associated with a write operation at an interface of the DRAM device;
storing the address in a buffer for a configurable period of time;
aborting the write operation if, within the configurable period of time, a determination is made that the address contains an error, wherein, in absence of an indication within the configurable period of time that the determination has been made, writing the data into a memory array of the DRAM device at the address; and
transmitting information from the DRAM device to the memory controller, wherein the information represents error in the address.

12. The method of claim 11 , further comprising within the configurable period of time, discarding the data without writing the data into the memory array if the error exists in the address.

13. The method of claim 11 , further comprising computing on-board the DRAM device a cyclic redundancy code (CRC) based on the data, the CRC to be used to determine whether there is error in the data.

14. The method of claim 11 , further comprising transmitting information to the memory controller representing error in the data.

15. The method of claim 14 , wherein the error information representing error in the data transmitted by the DRAM device to the memory controller is alone sufficient for the memory controller to differentiate an error in the address, if any, from an error in the data.

16. The method of claim 14 , further comprising:
receiving at the interface a command to retry the write operation; and
in response to the command, overwriting erroneous data which was written into the memory array at the address if the error information represents error in the associated data but not error in the address for a given write command.

17. The method of claim 11 , wherein:
queuing a number memory operations, including a write command and including a read command received after the write command; and
aborting the read command in the event of a determination made that an error exists in an address associated with the read command.

18. The method of claim 11 , wherein the method further comprises configuring the buffer according to the configurable period of time.

19. The method of claim 11 , wherein the method further comprises calibrating the configurable period of time during a start-up sequence, and responsively configuring the buffer according to the configurable period of time.

20. The method of claim 11 , wherein the determination that the error exists in the address is made by the memory controller, wherein the method further comprises receiving at the DRAM device, from the memory controller, the indication in the form of an abort command responsive to the determination, wherein the method further comprises writing the data into the memory array at the address in absence of the DRAM device receiving the abort command and, wherein further, the method further comprises configuring the buffer such that the configurable period of time is longer than a time required to transmit the error information to the memory controller, a time to make the determination, and a time for the memory controller to responsively transmit the abort command to the DRAM device.

21. A dynamic random access memory (DRAM) device, comprising:
an interface to receive an address and data associated with a write operation;
a memory array;
a buffer to store the address for a configurable period of time;
circuitry to abort the write operation if, within the configurable period of time, a determination is made that the address contains an error, wherein the circuitry is to, in absence of an indication within the configurable period of time that the determination has been made, write the data into the memory array at the address; and
a transmitter to transmit information to the memory controller representing error in the address, and representing error in the data;
wherein if error is determined to exist in the data, the DRAM device is to receive a write command from the memory controller to retry the write operation.

Assignees

• Rambus Inc

Inventors

• Shaeffer Ian
• Hampel Craig E

Classifications

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• G06F11/0703

  Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation · CPC title

• G06F11/1679

  at clock signal level · CPC title

• G06F11/073

  in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title