Diverse redundant processing modules for error detection

Patent metadata

Field	Value
Publication number	US-2020019477-A1
Application number	US-201816031813-A
Country	US
Kind code	A1
Filing date	Jul 10, 2018
Priority date	Jul 10, 2018
Publication date	Jan 16, 2020
Grant date	—

Abstract

In one embodiment, a system has an integrated circuit (IC) device, the IC device includes a first processing unit having a first functional block that has a diversifiable sub-circuit and a result output, a second processing unit having a second functional block substantially identical to the first functional block that includes a corresponding diversifiable sub-circuit and a corresponding result output. The IC device includes a comparator adapted to compare the result output of the first functional block to the result output of the second functional block. The diversifiable sub-circuit of the first functional block operates using a first set of operating parameters. The diversifiable sub-circuit of the second functional block operates using a second set of operating parameters different from the first set of operating parameters.

First claim

1 . A system comprising an integrated circuit (IC) device, the IC device comprising:
a first functional block comprising a diversifiable sub-circuit and adapted to output a result; a second functional block substantially identical to the first functional block, comprising a corresponding diversifiable sub-circuit and adapted to output a corresponding result; and a comparator adapted to compare the result output of the first functional block to the result output of the second functional block, wherein:
the diversifiable sub-circuit of the first functional block operates using a first set of operating parameters; and
the diversifiable sub-circuit of the second functional block operates using a second set of operating parameters different from the first set of operating parameters.

2 . The system of claim 1 , wherein:
the first and second functional blocks are adapted to receive identical inputs and process the inputs identically.

3 . The system of claim 1 , wherein the diversifiable sub-circuit comprises a power delivery network (PDN) for the corresponding functional block.

4 . The system of claim 3 , wherein:
the PDN comprises a block header-switch module; the block header-switch module has a variable resistance; and the first and second sets of operating parameters control the variable resistance of the corresponding block header-switch module to provide different core voltages to the first and second functional blocks.

5 . The system of claim 4 , wherein:
the block header-switch module comprises a plurality of transistors; operating the diversifiable sub-circuit of the first functional block using the first set of operating parameters results in a first number of transistors of the corresponding block header-switch module being on; and operating the diversifiable sub-circuit of the second functional block using the second set of operating parameters results in a second number of transistors of the corresponding block header-switch module, different from the first number, being on.

6 . The system of claim 3 , wherein:
the diversifiable sub-circuit comprises a block footer-switch module; the block footer-switch module has a variable resistance; and the first and second sets of operating parameters control the variable resistance of the corresponding block footer-switch module to provide different core voltages to the first and second functional blocks.

7 . The system of claim 1 , wherein the diversifiable sub-circuit comprises a clock delivery network (CDN) for the corresponding functional block.

8 . The system of claim 7 , wherein:
the CDN comprises a plurality of delay elements arranged in the form of a tree; the plurality of delay elements comprises a set of tunable delay elements; and the first and second operating parameters control the delays of the corresponding sets of tunable delay elements to provide different delays along selected paths of the first and second functional block.

9 . The system of claim 7 , wherein:
the diversifiable sub-circuit comprises:
a clock input to the corresponding functional block; and
a tunable RC filter having an RC constant and connected to the clock input; and
the first and second sets of operating parameters control the RC constant of the corresponding RC filters to have different RC constants so that the first and second functional block are sensitive to different frequencies of power-supply noise.

10 . The system of claim 9 , wherein the tunable RC filter comprises as least one of a tunable resistor and a tunable capacitor.

11 . The system of claim 1 , wherein the system is a vehicle.

12 . The system of claim 1 , wherein:
the device is a system on chip (SoC) device; the SoC comprises a first processing unit and a second processing unit; the first processing unit comprises the first functional block; and the second processing unit comprises the second functional block.

13 . A method for an integrated circuit (IC) device comprising a first functional block comprising a diversifiable sub-circuit and adapted to output a result, a second functional block substantially identical to the first functional block, comprising a corresponding diversifiable sub-circuit and adapted to output a corresponding result, and a comparator adapted to compare the result output of the first functional block to the result output of the second functional block, the method comprising:
operating the diversifiable sub-circuit of the first functional block using a first set of operating parameters; and operating the diversifiable sub-circuit of the second functional block using a second set of operating parameters different from the first set of operating parameters.

14 . The method of claim 13 , wherein:
the first and second functional blocks are adapted to receive identical inputs and process the inputs identically.

15 . The method of claim 13 , wherein the diversifiable sub-circuit comprises a power delivery network (PDN) for the corresponding functional block.

16 . The method of claim 15 , wherein:
the PDN comprises a block header-switch module; the block header-switch module has a variable resistance; and the method comprises the first and second sets of operating parameters controlling the variable resistance of the corresponding block header-switch module to provide different core voltages to the first and second functional blocks.

17 . The method of claim 16 , wherein:
the block header-switch module comprises a plurality of transistors; and the method comprises:
operating the diversifiable sub-circuit of the first functional block using the first set of operating parameters to have a first number of transistors of the corresponding block header-switch module on; and
operating the diversifiable sub-circuit of the second functional block using the second set of operating parameters to have a second number of transistors of the corresponding block header-switch module, different from the first number, on.

18 . The method of claim 16 , wherein:
the diversifiable sub-circuit comprises a block footer-switch module; the block footer-switch module has a variable resistance; and the method comprises the first and second sets of operating parameters controlling the variable resistance of the corresponding block footer-switch module to provide different core voltages to the first and second functional blocks.

19 . The method of claim 13 , wherein the diversifiable sub-circuit comprises a clock delivery network (CDN) of the corresponding functional block.

20 . The method of claim 19 , wherein:
the CDN comprises a plurality of delay elements arranged in the form of a tree; the plurality of delay elements comprises a set of tunable delay elements; and the method comprises the first and second operating parameters controlling the delays of the corresponding sets of tunable delay elements to provide different delays along selected paths of the first and second functional blocks.

21 . The method of claim 19 , wherein:
the diversifiable sub-circuit comprises:
a clock input to the corresponding functional block; and
a tunable RC filter having an RC constant and connected to the clock input; and
the method comprises the first and second sets of operating parameters controlling the RC constant of the corresponding RC filters to have different RC constants so that the first and second functional blocks are sensitive to different frequencies of power-supply noise.

22 . Th

Assignees

• Qualcomm Inc

Inventors

• Jain Palkesh
• Gulati Rahul

Classifications

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• G01R31/31703

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title

• G06F11/184

  where the redundant components implement processing functionality · CPC title

• G06F11/1645 Primary

  and the comparison itself uses redundant hardware · CPC title

• G06F11/1641

  where the comparison is not performed by the redundant processing components · CPC title