Integrated Circuit Chip with Cores Asymmetrically Oriented With Respect To Each Other

Patent metadata

Field	Value
Publication number	US-2020233758-A1
Application number	US-202016838176-A
Country	US
Kind code	A1
Filing date	Apr 2, 2020
Priority date	Sep 15, 2015
Publication date	Jul 23, 2020
Grant date	—

Abstract

An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

First claim

What is claimed is:

1 . A method, comprising:
disposing a first core having an output and a first orientation on a substrate; disposing a second core having an output and a second orientation on the substrate, the second core is a replica of the first core and the second orientation is different than the first orientation; and disposing a compare unit having a first input and a second input on the substrate, the first input coupled to the output of the first core and the second input coupled to the output of the second core.

2 . The method of claim 1 , wherein the second orientation is flipped with respect to the first orientation.

3 . The method chip of claim 1 , wherein the second orientation is rotated 180 degrees with respect to the first orientation.

4 . The method of claim 1 , wherein the second orientation is flipped and rotated 180 degrees with respect to the first orientation.

5 . The method of claim 1 , wherein a first data at the output of the first core a second data at the output of the second core are transmitted at substantially the same time.

6 . The method of claim 1 , further comprising a memory, wherein the first core and the second core are configured to access the memory.

7 . The method of claim 6 , further comprising a pipeline coupled between the memory and one of the first and the second cores.

8 . The method of claim 1 , further comprising a pipeline coupled between the compare unit and one of the first and the second cores.

9 . The method of claim 8 , wherein data transmitted from each of the first core and the second core arrives are transmitted at substantially the same time.

10 . The method of claim 1 , wherein the first core and the second core are configured to operate in lockstep.

11 . The method of claim 1 , wherein the first core and the second core are each general purpose processors configured to execute machine readable instructions.

12 . The method of claim 1 , wherein no point in space is equidistance from the same region of electrical components to both the first core and the second core

13 . A method, comprising:
providing a non-transitory machine readable memory configured to store data; providing a pair of matched cores configured to operate in lockstep, the pair of matched cores including a given core and another core, wherein the other core is a replica of the given core and is asymmetrically oriented with respect to the given core; and providing a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

14 . The method of claim 13 , wherein the orientation of the other core is rotated relative to the orientation of the given core.

15 . The method of claim 14 , wherein no point on the IC chip is equidistant from given regions of the given core and replicated regions of the given regions on the other core.

16 . The method of claim 13 , wherein no point in space is equidistance from the same region of electrical components to both the give core and the other core

17 . The method of claim 13 , wherein the given core and the other core are on a common substrate.

18 . The method of claim 13 , wherein the given core and the other core are formed on a same die.

19 . The method of claim 13 , wherein the given core is flipped with respect to the other core.

20 . The method chip of claim 13 , wherein the given core is rotated 180 degrees with respect to the other core.

21 . The method of claim 13 , wherein data transmitted from each of the given core and the other core arrive at the compare unit at substantially the same time.

22 . The method of claim 13 , further comprising a memory, wherein the given core and the other core are configured to access the memory.

23 . The method of claim 22 , further comprising a pipeline coupled between the memory and one of the given and the other cores.

24 . The method of claim 13 , further comprising a pipeline coupled between the compare unit and one of the given and the other cores.

25 . The method of claim 24 , wherein data transmitted from each of the given core and the other core arrives at the compare unit at substantially the same time.

26 . The method of claim 13 , wherein the given core and the other core are configured to operate in lockstep.

27 . The method of claim 13 , wherein the given core and the other core are each general purpose processors configured to execute machine readable instructions.

28 . The method of claim 13 , wherein no point in space is equidistance from the same region of electrical components to both the give core and the other core.

29 . An apparatus, comprising:
a first processor on a die having a first position and a first orientation; a second processor on the die that is a replica of the first processor, the second processor having a second position and a second orientation different from the first orientation; and a compare unit on the die to compare output signals from the first processor to output signals from the second processor.

30 . The apparatus of claim 29 , wherein the first and second processors are configured to operate in lockstep.

31 . The apparatus of claim 29 , further comprising a same set of instructions in each of the first and second processors in lockstep.

32 . The apparatus of claim 29 , wherein the second orientation is rotated with respect to the first orientation.

33 . The apparatus of claim 29 , wherein no point on the apparatus is equidistant from given regions of the first processor and replicated regions of the given regions on the second processor.

34 . The apparatus of claim 29 , wherein data transmitted from each of the first processor and the second processor arrive at the compare unit at substantially the same time.

35 . The apparatus of claim 29 further comprising a memory, wherein the first processor and the second processor are configured to access the memory.

36 . The apparatus of claim 29 , further comprising a pipeline coupled between a memory and one of the first processor and the second processor.

37 . The apparatus of claim 29 , further comprising a pipeline coupled between the compare unit and one of the first processor and the second processor.

38 . The apparatus of claim 29 , wherein the first processor and the second processor are configured to operate in lockstep.

39 . The apparatus of claim 29 , wherein the first processor and the second processor are each general purpose processors configured to execute machine readable instructions.

Assignees

• Texas Instruments Inc

Inventors

• Nayyar Jasbir Singh
• Nuthakki Shashank Srinivasa
• Gulati Rahul
• Shrimali Arun

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• G06F30/333

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title