Fault Tolerant Clock Monitor System

Patent metadata

Field	Value
Publication number	US-2019114235-A1
Application number	US-201816158471-A
Country	US
Kind code	A1
Filing date	Oct 12, 2018
Priority date	Oct 16, 2017
Publication date	Apr 18, 2019
Grant date	—

Abstract

A clock monitor includes a test clock input, as a reference clock input, another clock input, a measurement circuit, and control logic. The measurement circuit generates a measurement of a frequency or a duty cycle of the test clock input using the reference clock input, which is compared to a threshold. The control logic determines whether the measurement exceeded the threshold and, based on the measurement exceeding the threshold, cause generation of another measurement of a frequency or a duty cycle using the third clock input in combination with the first clock input or the reference clock input. The control logic may determine whether the other measurement exceeded a threshold and, based on such a determination, further determine that the test clock input or the reference clock input are faulty.

First claim

We claim:

1 . A clock monitor, comprising:
a first clock input, configured as a test clock input; a second clock input, configured as a reference clock input; a third clock input; a measurement circuit configured to generate a first measurement of a frequency or a duty cycle of the test clock input using the reference clock input; a comparator circuit configured to compare the first measurement to one or more thresholds; and control logic configured to:
determine whether the first measurement was below a lower limit or above an upper limit of one or more thresholds;
based on a determination that the first measurement was below a lower limit or above an upper limit of one or more thresholds, cause the measurement circuit to generate a second measurement of a frequency or a duty cycle using the third clock input in combination with the test clock input or the reference clock input;
determine whether the second measurement was below a lower limit or above an upper limit of one or more thresholds;
based on whether the second measurement was below a lower limit or above an upper limit of one or more thresholds, determine that the test clock input or the reference clock input are faulty.

2 . The clock monitor of claim 1 , wherein the control logic is further configured to select a backup clock to replace a clock source of the test clock input or the reference clock input based on the second measurement.

3 . The clock monitor of claim 1 , wherein the control logic is further configured to delay selection of a backup clock to replace a clock source of the test clock input or the reference clock input based on the first measurement.

4 . The clock monitor of claim 1 , where the thresholds include:
a first threshold, beyond which the control logic is configured to issue a warning signal while maintaining a clock source of the test clock input or the reference clock input; and a second threshold, beyond which the control logic is configured to issue a failure while selecting a backup clock to replace the clock source of the test clock input or the reference clock input.

5 . The clock monitor of claim 4 , wherein the warning signal includes an interrupt event for a processor and the failure includes a clock switch event configured to replace the clock source.

6 . The clock monitor of claim 1 , further comprising a backup clock select input to determine a backup clock from a plurality of clock candidates to replace a clock source of the test clock input or the reference clock input based on the second measurement.

7 . The clock monitor of claim 1 , wherein the control logic is further configured to adjust a period of time during which data is collected for measured clock inputs.

8 . The clock monitor of claim 1 , wherein the control logic is further configured to adjust accuracy for which data is collected for measured clock inputs.

9 . The clock monitor of claim 1 , wherein the control logic is further configured to cause the measurement circuit to generate the second measurement of a frequency or a duty cycle of the test clock input using the third clock input as a reference clock signal.

10 . The clock monitor of claim 1 , wherein the control logic is further configured to cause the measurement circuit to generate the second measurement of a frequency or a duty cycle of reference clock input using the third clock input as a reference clock.

11 . The clock monitor of claim 1 , wherein the control logic is further configured to select the test clock input and the reference clock input from three or more candidate clock signals.

12 . A method, comprising:
receiving a first clock input as a test clock input; receiving a second clock input as reference clock input; receiving a third clock input; generating a first measurement of a frequency or a duty cycle of the test clock input using the reference clock input; comparing the first measurement to one or more thresholds; determining whether the first measurement was below a lower limit or above an upper limit of one or more thresholds; based on a determination that the first measurement was below a lower limit or above an upper limit of one or more thresholds, causing the measurement circuit to generate a second measurement of a frequency or a duty cycle using the third clock input in combination with the test clock input or the reference clock input; determining whether the second measurement was below a lower limit or above an upper limit of one or more thresholds; and based on whether the second measurement was below a lower limit or above an upper limit of one or more thresholds, determining that the test clock input or the reference clock input are faulty.

13 . The method of claim 12 , further comprising selecting a backup clock to replace a clock source of the test clock input or the reference clock input based on the second measurement.

14 . The method of claim 12 , further comprising delaying selection of a backup clock to replace a clock source of the test clock input or the reference clock input based on the first measurement.

15 . The method of claim 12 , where the thresholds include:
a first threshold, beyond the method includes issuing a warning signal while maintaining a clock source of the test clock input or the reference clock input; and a second threshold, beyond which the method includes issuing a failure while selecting a backup clock to replace the clock source of the test clock input or the reference clock input.

16 . The method of claim 15 , wherein the warning signal includes an interrupt event for a processor and the failure includes a clock switch event to replace the clock source.

17 . The method of claim 12 , further comprising receiving a backup clock select input to determine a backup clock from a plurality of clock candidates to replace a clock source of the test clock input or the reference clock input based on the second measurement.

18 . The method of claim 12 , further comprising generating the second measurement of a frequency or a duty cycle of the test clock input using the third clock input as a reference clock signal.

19 . The method of claim 12 , further comprising generating the second measurement of a frequency or a duty cycle of reference clock input using the third clock input as a reference clock.

20 . The method of claim 12 , further comprising selecting the test clock input and the reference clock input from three or more candidate clock signals.

Assignees

• Microchip Tech Inc

Inventors

• Wojewoda Igor
• Kris Bryan
• Bowling Stephen
• Yuenyongsgool Yong

Classifications

• H03K5/19 Primary

  Monitoring patterns of pulse trains (indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02) · CPC title

• G06F11/1679

  at clock signal level · CPC title

• G06F11/1604 Primary

  where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware · CPC title

• G06F11/142

  Reconfiguring to eliminate the error (group management mechanisms in a peer-to-peer network H04L67/1044) · CPC title

• G06F11/3419

  by assessing time · CPC title