Overlay and semiconductor process control using a wafer geometry metric

US9354526B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9354526-B2
Application numberUS-201213476328-A
CountryUS
Kind codeB2
Filing dateMay 21, 2012
Priority dateOct 11, 2011
Publication dateMay 31, 2016
Grant dateMay 31, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables, defining a plurality of metric analysis regions distributed across the surface, and then generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region.

First claim

Opening claim text (preview).

What is claimed: 1. A method for providing a wafer geometry metric, comprising: acquiring a wafer shape value at each of a plurality of points of a surface of a wafer at a first process level and an additional process level; generating a wafer shape change value at each of the points utilizing the acquired wafer shape value at each of the points at the first process level and the additional process level, the wafer shape change value at each point corresponding to a change in wafer shape between the first process level and the second process level; generating a set of slope of shape change values by calculating a slope of shape change at each of the points utilizing the generated wafer shape change value at each of the points, each of the slope of shape change values corresponding to a slope of the change in wafer shape along at least one direction of the surface of the wafer; calculating a set of process tool correctables utilizing the generated set of slope of shape change values; generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables; defining a plurality of metric analysis regions distributed across the surface of the wafer, each metric analysis region encompassing one or more points of the plurality of points; and generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region. 2. A method for providing a wafer geometry metric, comprising: acquiring a wafer shape value at each of a plurality of points of a surface of the wafer at a process level; generating a set of slope of shape values by calculating a slope of shape value at each of the points at the process level utilizing the wafer shape values acquired at the process level; calculating a set of process tool correctables utilizing the generated set of slope of shape values; generating a set of slope shape residuals (SSRs) by calculating a slope of shape residual value at each of the points utilizing the set of process tool correctables; defining a plurality of metric analysis regions distributed across the surface of the wafer, each metric analysis region encompassing one or more points of the plurality of points; and generating one or more residual slope shape metrics for each metric analysis region based on one or more SSRs within each metric analysis region. 3. The method of claim 2 , wherein the calculated slope of shape value value at each of the points comprises: at least one of a front-side wafer surface shape slope or a back-side wafer surface shape slope. 4. The method of claim 2 , further comprising: generating a global residual slope shape metric for the wafer utilizing the one or more residual slope shape change metrics for each metric analysis region. 5. The method of claim 2 , wherein the generating one or more residual slope shape metrics for each metric analysis region based on one or more SSRs within each metric analysis region comprises: generating a residual slope shape mean metric for each metric analysis region based on one or more SSRs within each metric analysis region. 6. The method of claim 2 , wherein the generating one or more residual slope shape metrics for each metric analysis region based on one or more SSRs within each metric analysis region comprises: generating a residual slope shape deviation metric for each metric analysis region based on one or more SSRs within each metric analysis region. 7. The method of claim 2 , wherein the generating one or more residual slope shape metrics for each metric analysis region based on one or more SSRs within each metric analysis region comprises: generating a residual slope shape range metric for each metric analysis region based on one or more SSRs within each metric analysis region. 8. The method of claim 2 , wherein the generating one or more residual slope shape metrics for each metric analysis region based on one or more SSRs within each metric analysis region comprises: generating a residual slope shape maximum metric for each metric analysis region based on one or more SSRs within each metric analysis region. 9. The method of claim 2 , further comprising: generating one or more residual overlay metrics for each metric analysis region based on one or more residual overlay values within each metric analysis region. 10. The method of claim 2 , wherein the calculating a set of process tool correctables utilizing the generated set of slope of shape values comprises: calculating at least one of a set of wafer-level process tool correctables utilizing the generated set of slope of shape values or a set of field-level process tool correctables utilizing the generated set of slope of shape values. 11. The method of claim 2 , wherein the calculating a set of process tool correctables utilizing the generated set of slope of shape values comprises: calculating at least one of a set of linear process tool correctables utilizing the generated set of slope of shape values or a set of higher-order process tool correctables utilizing the generated set of slope of shape values. 12. A system for providing a wafer geometry metric, comprising: a topography system configured to perform a set of topography measurements in order to acquire a wafer shape value at each of a plurality of points of a surface of a wafer at a first process level and an additional process level; and one or more computing systems communicatively coupled to the topography and configured to receive the set of topography measurements, the one or more computing systems further configured to: generate a wafer shape change value at each of the points utilizing the acquired wafer shape value at each of the points at the first process level and the additional process level; generate a set of slope of shape change values by calculating a slope of shape change at each of the points utilizing the generated wafer shape change value at each of the points; calculating a set of process tool correctables utilizing the generated set of slope of shape change values; generating a set of slope shape change residuals (SSCRs) by calculating a slope of shape change residual value at each of the points utilizing the set of process tool correctables; defining a plurality of metric analysis regions distributed across the surface of the wafer; and generating one or more residual slope shape change metrics for each metric analysis region based on one or more SSCRs within each metric analysis region. 13. The system of claim 12 , wherein the topography systems comprises: an interferometry based topography system. 14. The system of claim 13 , wherein the interferometry based topography system comprises: a dual Fizeau interferometer. 15. The system of claim 12 , wherein the topography system comprises: a topography system configured to measure a front-side surface of the wafer and the back-side surface of the wafer simultaneously. 16. The system of claim 12 , wherein the generated wafer shape change value at each of the points comprises: at least one of a front-side wafer surface shape change or a back-side wafer surface shape change. 17. The system of claim 12 , wherein the wafer shape value at each of a plurality of points of a surface of a wafer at a first process level and an additional process level comprises is acquired by: receiving a wafer in a substantially free state; performing a first set topographic measurements on the wafer at a first proc

Assignees

Inventors

Classifications

  • Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • Sorting devices · CPC title

  • Monitoring of warpages, curvatures, damages, defects or the like · CPC title

  • Handling stress or warp of chucks, masks or workpieces, e.g. to compensate for imaging errors or considerations related to warpage of masks or workpieces due to their own weight · CPC title

  • Two or more interferometric channels or interferometers · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9354526B2 cover?
The present invention may include acquiring a wafer shape value at a plurality of points of a wafer surface at a first and second process level, generating a wafer shape change value at each of the points, generating a set of slope of shape change values at each of the points, calculating a set of process tool correctables utilizing the generated set of slope of shape change values, generating …
Who is the assignee on this patent?
Vukkadala Pradeep, Veeraraghavan Sathish, Sinha Jaydeep K, and 1 more
What technology area does this patent fall under?
Primary CPC classification H10P72/0616. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 31 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).