Overlay and semiconductor process control using a wafer geometry metric
US-9354526-B2 · May 31, 2016 · US
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Veeraraghavan Sathish patents
Veeraraghavan Sathish holds 1 patent in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 1 |
| Recent patents | 0 |
| First publication | May 31, 2016 |
| Latest publication | May 31, 2016 |
Filing trend
Year-over-year patent counts for this assignee.
Not enough yearly data to assess filing trend yet.
| Year | Patents |
|---|---|
| 2016 | 1 |
| Year | Patents |
|---|---|
| 2016 | 1 |
Recent patents
Latest publications where this party is an assignee.
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Top CPC classifications
Most common classification codes in this portfolio.
| CPC | Patents |
|---|---|
| H10P74/203 | 1 |
| H10P72/0611 | 1 |
| H10P72/0616 | 1 |
| G03F7/70783 | 1 |
| G01B9/02027 | 1 |
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Physics | 1 |
| Electricity | 1 |