Package comprising dummy silicon structure located between integrated devices

Patent metadata

Field	Value
Publication number	US-2025391755-A1
Application number	US-202418748011-A
Country	US
Kind code	A1
Filing date	Jun 19, 2024
Priority date	Jun 19, 2024
Publication date	Dec 25, 2025
Grant date	—

Abstract

A package comprising a package interposer, a first integrated device coupled to the package interposer, a second integrated device coupled to the package interposer, a dummy silicon structure located laterally between the first integrated device and the second integrated device, and a second encapsulation layer coupled to the package interposer, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device and the dummy silicon structure. The package interposer comprises a first metallization portion; a second metallization portion; a first passive device located between the first metallization portion and the second metallization portion; and a first encapsulation layer located between the first metallization portion and the second metallization portion.

First claim

1 . A package comprising:
a package interposer comprising:
a first metallization portion;
a second metallization portion;
a first passive device located between the first metallization portion and the second metallization portion; and
a first encapsulation layer located between the first metallization portion and the second metallization portion;
a first integrated device coupled to the package interposer; a second integrated device coupled to the package interposer; a dummy silicon structure located laterally between the first integrated device and the second integrated device; and a second encapsulation layer coupled to the package interposer, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device and the dummy silicon structure.

2 . The package of claim 1 , wherein the dummy silicon structure is coupled to the package interposer through an adhesive.

3 . The package of claim 1 , wherein the dummy silicon structure is configured to be free of any electrical connection with the first integrated device and/or the second integrated device.

4 . The package of claim 1 , wherein the package interposer further comprises a second dummy silicon structure located laterally between the first integrated device and the second integrated.

5 . The package of claim 1 , wherein the dummy silicon structure is located adjacent to (i) an edge of the first integrated device comprising a die to die portion, and (ii) an edge of the second integrated device comprising a die to die portion.

6 . The package of claim 1 ,
wherein the first integrated device is coupled to the package interposer through a first plurality of pillar interconnects and/or a first plurality of solder interconnects, and
wherein the second integrated device is coupled to the package interposer through a second plurality of pillar interconnects and/or a second plurality of solder interconnects.

7 . The package of claim 1 ,
wherein the first integrated device is coupled to the first metallization portion of the package interposer, and
wherein the second integrated device is coupled to the first metallization portion of the package interposer.

8 . The package of claim 1 ,
wherein the first integrated device is coupled to the second metallization portion of the package interposer, and
wherein the second integrated device is coupled to the second metallization portion of the package interposer.

9 . The package of claim 1 , wherein the first passive device includes a trench capacitor device.

10 . The package of claim 1 ,
wherein the package interposer further comprises a second passive device,
wherein the first passive device is configured to be electrically coupled to the first integrated device, and
wherein the second passive device is configured to be electrically coupled to the second integrated device.

11 . The package of claim 1 , wherein the package interposer further comprises a bridge located between the first metallization portion and the second metallization portion.

12 . The package of claim 11 , wherein an electrical path between the first integrated device and the second integrated device includes the bridge.

13 . The package of claim 11 , wherein an electrical path between the first integrated device and the second integrated device includes the bridge and the first metallization portion.

14 . The package of claim 11 , wherein an electrical path between the first integrated device and the second integrated device includes the bridge and the second metallization portion.

15 . The package of claim 1 , wherein the package implemented in a device from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.

16 . A package comprising:
a substrate; a first integrated device coupled to the substrate; a second integrated device coupled to the substrate; a dummy silicon structure located laterally between the first integrated device and the second integrated device; and an encapsulation layer coupled to the substrate, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device and the dummy silicon structure.

17 . The package of claim 16 , wherein the dummy silicon structure is coupled to the substrate through an adhesive.

18 . The package of claim 16 ,
wherein the first integrated device is coupled to the substrate through a first plurality of pillar interconnects and/or a first plurality of solder interconnects, and
wherein the second integrated device is coupled to the substrate through a second plurality of pillar interconnects and/or a second plurality of solder interconnects.

19 . A package comprising:
a metallization portion; a first integrated device coupled to the metallization portion; a second integrated device coupled to the metallization portion; a dummy silicon structure located laterally between the first integrated device and the second integrated device; and an encapsulation layer coupled to the metallization portion, wherein the encapsulation layer at least partially encapsulates the first integrated device, the second integrated device and the dummy silicon structure.

20 . The package of claim 19 , wherein the dummy silicon structure touches the metallization portion.

Assignees

• Qualcomm Inc

Inventors

• Song Yanmei
• Stone William

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W74/131

  the semiconductor body being only partially enclosed · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title