Semiconductor device package having dummy dies

Patent metadata

Field	Value
Publication number	US-2022384390-A1
Application number	US-202217817705-A
Country	US
Kind code	A1
Filing date	Aug 5, 2022
Priority date	Nov 13, 2020
Publication date	Dec 1, 2022
Grant date	—

Abstract

A semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.

First claim

What is claimed is:

1 . A semiconductor device package, comprising:
a substrate; a first package component and a second package component disposed over and bonded to the substrate, wherein the first and second package components are different types of electronic components that provide different functions; and at least one dummy die disposed over and attached to the substrate, wherein the dummy die is between the first and second package components and is electrically isolated from the substrate.

2 . The semiconductor device package as claimed in claim 1 , wherein the dummy die is substantially free of any functional circuitry.

3 . The semiconductor device package as claimed in claim 1 , wherein there is a first gap formed between the first and second package components and extending in a first direction, and the dummy die extends in the first direction with a second gap formed between the dummy die and the first package component and a third gap formed between the dummy die and the second package component, wherein the second and third gaps are smaller than the first gap.

4 . The semiconductor device package as claimed in claim 3 , wherein the at least one dummy die includes a plurality of dummy dies, and the dummy dies are arranged in the first direction.

5 . The semiconductor device package as claimed in claim 1 , further comprising:
a plurality of electrical connectors disposed between the first package component and the substrate and between the second package component and the substrate for electrically connecting the first and second package components to the substrate; an attaching structure disposed between the dummy die and the substrate for attaching the dummy die to the substrate; and an underfill element configured to surround the electrical connectors and the attaching structure.

6 . The semiconductor device package as claimed in claim 5 , wherein the underfill element extends up along sidewalls of the dummy die, and a top surface of the dummy die is exposed from the underfill element.

7 . The semiconductor device package as claimed in claim 5 , wherein the dummy die has a greater modulus of elasticity than the underfill element.

8 . The semiconductor device package as claimed in claim 1 , wherein the dummy die has a first portion between adjacent sidewalls of the first and second package components and a second portion extending to top surfaces of the first and second package components.

9 . The semiconductor device package as claimed in claim 1 , further comprising a ring disposed over the substrate and surrounding the first and second package components and the dummy die.

10 . A semiconductor device package, comprising:
a substrate having a first surface; a first package component and a second package component bonded to the first surface, wherein the first and second package components are different types of electronic components that provide different functions; and a dummy die attached to the first surface, wherein the dummy die is in a gap between the first and second package components and is electrically isolated from the substrate, wherein a coefficient of thermal expansion (CTE) of the dummy die is similar to that of the substrate.

11 . The semiconductor device package as claimed in claim 10 , wherein the dummy die is bulk metal, with the entirety formed of a homogeneous high-modulus material, and the high-modulus material comprises copper or stainless steel.

12 . The semiconductor device package as claimed in claim 10 , wherein a height of the dummy die is less than a height of the first package component or the second package component in a direction perpendicular to the first surface.

13 . The semiconductor device package as claimed in claim 10 , wherein sidewalls of the dummy die are inclined relative to the first surface, and a top surface of the dummy die has a greater size than a bottom surface of the dummy die.

14 . The semiconductor device package as claimed in claim 10 , wherein sidewalls of the dummy die are inclined relative to the first surface, and a bottom surface of the dummy die has a greater size than a top surface of the dummy die.

15 . The semiconductor device package as claimed in claim 10 , further comprising an underfill element disposed between the substrate, the first package component, the second package component and the dummy die, wherein the dummy die has a greater modulus of elasticity than the underfill element.

16 . The semiconductor device package as claimed in claim 15 , wherein the dummy die is buried in the underfill element, and top surfaces of the first and second package components are exposed from the underfill element.

17 . A semiconductor device package, comprising:
a substrate; a first package component and a second package component disposed over and bonded to the substrate; at least one dummy die disposed over and attached to the substrate, wherein the dummy die is between the first and second package components and is electrically isolated from the substrate; and an underfill element disposed between the first package component, the second package component and the at least one dummy die, wherein the dummy die has a greater modulus of elasticity than the underfill element.

18 . The semiconductor device package as claimed in claim 17 , further comprising:
a plurality of electrical connectors disposed between the first package component and the substrate and between the second package component and the substrate for electrically connecting the first and second package components to the substrate, wherein the underfill element is also disposed to surround the electrical connectors.

19 . The semiconductor device package as claimed in claim 17 , wherein the at least one dummy die comprises silicon, copper or stainless steel.

20 . The semiconductor device package as claimed in claim 17 , wherein the at least one dummy die is substantially free of any functional circuitry.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Che-Chia
• Yeh Shu-Shen
• Lai Po-Chen
• Yew Ming-Chih
• Lin Po-Yao
• Jeng Shin-Puu

Classifications

• H10W90/725

  between a chip and a laterally-adjacent insulating package substrate, interposer or RDL · CPC title

• H10W74/141

  the encapsulations being on at least the sidewalls of the semiconductor body · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title