Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-2019096825-A1
Application number	US-201815938181-A
Country	US
Kind code	A1
Filing date	Mar 28, 2018
Priority date	Sep 27, 2017
Publication date	Mar 28, 2019
Grant date	—

Abstract

A fan-out semiconductor package includes a wiring portion, semiconductor chips, a dummy chip, and an encapsulant. The wiring portion includes an insulating layer, conductive patterns formed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns. The semiconductor chips are disposed on one region of the wiring portion, and the dummy chip is disposed on another region thereof and has a thickness smaller than those of the semiconductor chips. The encapsulant encapsulates at least portions of the semiconductor chips and the dummy chip. An upper surface of the wiring portion is disposed below a center line of the fan-out semiconductor package, and the thickness t of the dummy chip is such that T/2≤t≤3T/2 in which T is a distance from the upper surface of the wiring portion to the center line of the fan-out semiconductor package.

First claim

1 . A fan-out semiconductor package comprising:
a wiring portion including an insulating layer, conductive patterns formed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns; semiconductor chips disposed on one region of the wiring portion; at least one dummy chip disposed on another region of the wiring portion and having a thickness smaller than those of the semiconductor chips; and an encapsulant disposed on the wiring portion and encapsulating at least portions of the semiconductor chips and the at least one dummy chip, wherein an upper surface of the wiring portion is disposed below a center line of the fan-out semiconductor package, and the thickness t of the at least one dummy chip is such that T/2≤t≤3T/2 in which T is a distance from the upper surface of the wiring portion to the center line of the fan-out semiconductor package.

2 . The fan-out semiconductor package of claim 1 , wherein one surface of each of the semiconductor chips is exposed from the encapsulant.

3 . The fan-out semiconductor package of claim 2 , wherein the semiconductor chips each include an active surface on which connection pads are disposed and an inactive surface opposite to the active surface,
the inactive surfaces are exposed from the encapsulant, and a space between each dummy chip of the at least one dummy chip and the wiring portion is free of the encapsulant and free of any semiconductor chip.

4 . The fan-out semiconductor package of claim 2 , wherein a plurality of semiconductor chips are provided, and
one surface of each of the plurality of semiconductor chips is exposed from the encapsulant.

5 . The fan-out semiconductor package of claim 4 , wherein each of the at least one dummy chip is disposed between semiconductor chips of the plurality of semiconductor chips.

6 . The fan-out semiconductor package of claim 1 , wherein a plurality of dummy chips are provided.

7 . The fan-out semiconductor package of claim 6 , wherein the thickness of each of the plurality of dummy chips is the same as T.

8 . The fan-out semiconductor package of claim 1 , wherein the at least one dummy chip includes the same semiconductor material as the semiconductor chips.

9 . The fan-out semiconductor package of claim 1 , wherein the at least one dummy chip has a thermal expansion coefficient lower than that of the encapsulant.

10 . The fan-out semiconductor package of claim 1 , wherein the at least one dummy chip does not include connection pads.

11 . The fan-out semiconductor package of claim 1 , wherein the at least one dummy chip does not include wiring structures therein.

12 . A fan-out semiconductor package comprising:
a wiring portion including an insulating layer and at least one conductive pattern; a semiconductor chip disposed on an upper surface of the wiring portion and electrically connected to the at least one conductive pattern of the wiring portion; a dummy die disposed on the upper surface of the wiring portion; and an encapsulant disposed on the upper surface of the wiring portion and surrounding at least portions of the semiconductor chip and the dummy die, wherein a thickness t of the dummy die is such that T/2≤t≤3T/2 where T=(t 1 / 2 )−t 2 where t 1 is a thickness of the fan-out semiconductor package and t 2 is a thickness of the wiring portion.

13 . The fan-out semiconductor package of claim 12 , further comprising a plurality of semiconductor chips including the semiconductor chip,
wherein the dummy die is disposed between at least two semiconductor chips of the plurality of semiconductor chips on the upper surface of the wiring portion.

14 . The fan-out semiconductor package of claim 13 , further comprising a plurality of dummy dies including the dummy die,
wherein each dummy die of the plurality of dummy dies is disposed between at least two semiconductor chips of the plurality of semiconductor chips on the upper surface of the wiring portion.

15 . The fan-out semiconductor package of claim 12 , wherein the semiconductor chip includes one or more electronic component therein, and the dummy die is free of any electronic component therein.

16 . The fan-out semiconductor package of claim 12 , wherein the semiconductor chip includes a plurality of wiring patterns therein, and the dummy die is free of any wiring patterns therein, and
a space between the dummy die and the wiring portion is free of the encapsulant and free of any semiconductor chip.

17 . The fan-out semiconductor package of claim 12 , further comprising at least one bonding part disposed between a connection pad of the semiconductor chip and the upper surface of the wiring portion,
wherein a space between the dummy die and the upper surface of the wiring portion is free of any bonding part.

18 . The fan-out semiconductor package of claim 12 , wherein the at least one conductive pattern of the wiring portion provides an electrical connection between a connection pad of the semiconductor chip and a conductive pattern exposed on a lower surface of the wiring portion opposite to the upper surface thereof.

19 . The fan-out semiconductor package of claim 12 , wherein t 2 is a distance from the upper surface of the wiring portion to a lower surface of the wiring portion opposite to the upper surface thereof, and t 1 is a distance from the lower surface of the wiring portion to an upper surface of the semiconductor chips facing away from the wiring portion.

20 . The fan-out semiconductor package of claim 12 , wherein the dummy die is a dummy chip including a same semiconductor material as the semiconductor chip.

Assignees

• Samsung Electro Mech

Inventors

• Kim Jong Man
• Kim Han
• Lee Kyung Ho

Classifications

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00 Primary

  Package configurations · CPC title