Package comprising dummy silicon structure located between integrated devices
US-2026068780-A1 · Mar 5, 2026 · US
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Stone William patents
Stone William is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Stone William |
| Total patents | 21 |
| First publication | Nov 5, 2015 |
| Latest publication | Mar 5, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Package comprising integrated device and a metallization portion
US-2026011674-A1 · Jan 8, 2026 · US
Device comprising a package, a lid frame, a thermal interface material and an adhesive
US-2026005076-A1 · Jan 1, 2026 · US
Package comprising a passive device with variable sized bump interconnects
US-2026005176-A1 · Jan 1, 2026 · US
Package comprising a package interposer and a lid frame with an opening
US-2026005210-A1 · Jan 1, 2026 · US
Package comprising dummy silicon structure located between integrated devices
US-2025391755-A1 · Dec 25, 2025 · US
Package comprising a passive device with a front side protection layer
US-2025357448-A1 · Nov 20, 2025 · US
Package comprising an interposer package with metallization portions, and a passive device and a bridge between the metallization portions
US-2025343176-A1 · Nov 6, 2025 · US
Binder jetting print carriage
US-2025144875-A1 · May 8, 2025 · US
Integrated circuit (ic) packages employing a capacitor-embedded, redistribution layer (rdl) substrate for interfacing an ic chip(s) to a package substrate, and related methods
US-2025118645-A1 · Apr 10, 2025 · US
Recent patents
Latest publications not already listed above.
Package comprising a substrate with an embedded frame
US-2025069965-A1 · Feb 27, 2025 · US
Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods
US-12218041-B2 · Feb 4, 2025 · US
Package comprising a chiplet located between an integrated device and a metallization portion
US-2024072032-A1 · Feb 29, 2024 · US
Package comprising a chiplet located between two metallization portions
US-2024071993-A1 · Feb 29, 2024 · US
Package comprising integrated devices coupled through a metallization layer
US-11784157-B2 · Oct 10, 2023 · US
Package comprising integrated devices coupled through a metallization layer
US-2022392867-A1 · Dec 8, 2022 · US
Integrated circuit (ic) packages employing a capacitor-embedded, redistribution layer (rdl) substrate for interfacing an ic chip(s) to a package substrate, and related methods
US-2022344250-A1 · Oct 27, 2022 · US
Package on package (PoP) device comprising thermal interface material (TIM) in cavity of an encapsulation layer
US-10002857-B2 · Jun 19, 2018 · US
PACKAGE ON PACKAGE (PoP) DEVICE COMPRISING THERMAL INTERFACE MATERIAL (TIM) IN CAVITY OF AN ENCAPSULATION LAYER
US-2017294422-A1 · Oct 12, 2017 · US
Wafer level package without sidewall cracking
US-9318405-B2 · Apr 19, 2016 · US
Wafer level package and fan out reconstitution process for making the same
US-2015318229-A1 · Nov 5, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 20 |
| Desktop Metal Inc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/701 | 15 |
| H10W70/685 | 14 |
| H10W90/00 | 14 |
| H10W90/401 | 13 |
| H10W90/724 | 13 |