Package comprising an integrated device, a chiplet and a metallization portion

Patent metadata

Field	Value
Publication number	US-2024105688-A1
Application number	US-202217952163-A
Country	US
Kind code	A1
Filing date	Sep 23, 2022
Priority date	Sep 23, 2022
Publication date	Mar 28, 2024
Grant date	—

Abstract

A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects, a first chiplet coupled to the substrate, a second chiplet coupled to the first chiplet, an encapsulation layer coupled to the substrate, the first chiplet and the second chiplet, a plurality of encapsulation interconnects located in the encapsulation layer, a metallization portion coupled to the encapsulation layer, the second chiplet and the plurality of encapsulation interconnects and a first integrated device coupled to the metallization portion.

First claim

1 . A package comprising:
a substrate comprising at least one dielectric layer and a plurality of interconnects; a first chiplet coupled to the substrate; a second chiplet coupled to the first chiplet; an encapsulation layer coupled to the substrate, the first chiplet and the second chiplet; a plurality of encapsulation interconnects located in the encapsulation layer; a metallization portion coupled to the encapsulation layer, the second chiplet and the plurality of encapsulation interconnects; and a first integrated device coupled to the metallization portion.

2 . The package of claim 1 ,
wherein the first chiplet includes a first front side and a first back side, wherein the second chiplet includes a second front side and a second back side, and wherein the first front side of the first chiplet is coupled to the second front side of the second chiplet.

3 . The package of claim 1 ,
wherein the first chiplet includes a first plurality of through substrate vias, and wherein the second chiplet includes a second plurality of through substrate vias.

4 . The package of claim 1 , further comprising a third chiplet coupled to the substrate.

5 . The package of claim 4 , wherein the second chiplet is coupled to the third chiplet.

6 . The package of claim 5 ,
wherein the first chiplet includes a first front side and a first back side, wherein the second chiplet includes a second front side and a second back side, wherein the second chiplet includes a third front side and a third back side, wherein the first front side of the first chiplet is coupled to the second front side of the second chiplet, and wherein the third front side of the third chiplet is coupled to the second front side of the second chiplet.

7 . The package of claim 6 , wherein the third chiplet includes a deep trench capacitor.

8 . The package of claim 4 , wherein the first chiplet is coupled to the third chiplet.

9 . The package of claim 8 ,
wherein the first chiplet includes a first front side and a first back side, wherein the second chiplet includes a second front side and a second back side, wherein the second chiplet includes a third front side and a third back side, wherein the first front side of the first chiplet is coupled to the second front side of the second chiplet, and wherein the third front side of the third chiplet is coupled to the first front side of the first chiplet.

10 . The package of claim 1 , wherein an electrical path between the substrate and the first integrated device includes interconnects from the first chiplet and interconnects from the second chiplet.

11 . A package comprising:
a first metallization portion; a first chiplet coupled to the first metallization portion; an encapsulation layer coupled to the first metallization portion, the first chiplet; a plurality of encapsulation interconnects located in the encapsulation layer; a second metallization portion coupled to the encapsulation layer, the first chiplet, and the plurality of encapsulation interconnects; a second chiplet coupled to the second metallization portion; and a first integrated device coupled to the second chiplet and the second metallization portion such that the second chiplet is located between the first integrated device and the second metallization portion, wherein the first integrated device is coupled to the second chiplet through a plurality of solder interconnects.

12 . The package of claim 11 ,
wherein the first chiplet includes a first front side and a first back side, wherein the second chiplet includes a second front side and a second back side, and wherein the first front side of the first chiplet is coupled to the second metallization portion through a first plurality of solder interconnects, and wherein the second front side of the second chiplet is coupled to the second metallization portion through a second plurality of solder interconnects.

13 . The package of claim 11 , wherein the first chiplet and the second chiplet are configured to be coupled to a power distribution network.

14 . A device comprising:
a package comprising:
a substrate comprising at least one dielectric layer and a plurality of interconnects;
a bridge located in the substrate;
a first chiplet coupled to the substrate;
a second chiplet;
an encapsulation layer coupled to the substrate, the first chiplet and the second chiplet;
a plurality of encapsulation interconnects located in the encapsulation layer;
a metallization portion coupled to the encapsulation layer, the second chiplet and the plurality of encapsulation interconnects; and
a first integrated device coupled to the metallization portion.

15 . The device of claim 14 ,
wherein the first chiplet includes a first front side and a first back side, and wherein the first front side of the first chiplet is coupled to the bridge located in the substrate.

16 . The device of claim 14 , wherein at least one encapsulation interconnect from the plurality of encapsulation interconnects is coupled to the bridge.

17 . The device of claim 14 , wherein at least one encapsulation interconnect from the plurality of encapsulation interconnects is coupled to the second chiplet.

18 . The device of claim 14 , wherein the first chiplet is configured to be coupled to a power distribution network.

19 . The device of claim 14 , wherein the first chiplet and/or the second chiplet includes a deep trench capacitor.

20 . The device of claim 14 , wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.

Assignees

• Qualcomm Inc

Inventors

• Li Xia
• Zhang Xuefeng
• Patil Aniket

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title