Semiconductor device and method of manufacture

Patent metadata

Field	Value
Publication number	US-10879183-B2
Application number	US-201916272373-A
Country	US
Kind code	B2
Filing date	Feb 11, 2019
Priority date	Jun 22, 2018
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

A device includes a redistribution structure, a semiconductor device on the redistribution structure, a top package over the semiconductor device, the top package including a second semiconductor device, a molding compound interposed between the redistribution structure and the top package, a set of through vias between and electrically connecting the top package to the redistribution structure, and an interconnect structure disposed within the molding compound and electrically connecting the top package to the redistribution structure, the interconnect structure including a substrate and a passive device formed in the substrate, wherein the interconnect structure is free of active devices.

First claim

What is claimed is:

1. A device comprising:
a redistribution structure;
a first semiconductor device on the redistribution structure;
a top package over the first semiconductor device, the top package comprising a second semiconductor device;
a molding compound interposed between the redistribution structure and the top package;
a first set of through vias between and electrically connecting the top package to the redistribution structure;
a first interconnect structure disposed within the molding compound and electrically connecting the top package to the redistribution structure, the first interconnect structure comprising a substrate and a passive device formed in the substrate, wherein the substrate is free of active devices, wherein the first interconnect structure is different from the first semiconductor device; and wherein an integrated passive device coupled to the redistribution structure opposite the top package.

2. The device of claim 1 , wherein the passive device comprises a trench capacitor.

3. The device of claim 1 , the first interconnect structure further comprising:
a first through via extending through the substrate, the first through via being electrically connected to the second semiconductor device; and
a second through via extending through the substrate, the second through via being electrically connected to the second semiconductor device, wherein a first electrode of the passive device is electrically connected to the first through via and a second electrode of the passive device is electrically connected to the second through via.

4. The device of claim 3 , wherein the first interconnect structure further comprises a conductive trace, and wherein the conductive trace electrically connects the passive device and a third through via extending through the substrate.

5. The device of claim 1 , further comprising a polymer layer extending over the first interconnect structure, the first set of through vias, and the first semiconductor device.

6. The device of claim 1 , wherein the first interconnect structure further comprises a polymer layer disposed over the passive device, the first through via, and the second through via.

7. The device of claim 1 , further comprising a second interconnect structure between the top package and the redistribution structure, the second interconnect structure separated from the first semiconductor device, from the first interconnect structure, and from the first set of through vias by the molding compound.

8. The device of claim 1 , wherein at least one through via of the first set of through vias is disposed laterally between the first interconnect structure and the first semiconductor device.

9. A device comprising:
a redistribution structure;
a package comprising a first semiconductor device and a second semiconductor device disposed on a package substrate, the package disposed over the redistribution structure;
a third semiconductor device disposed between the redistribution structure and the package substrate and electrically connected to the redistribution structure;
a via extending between the redistribution structure and the package substrate, the via electrically connecting the redistribution structure to the package substrate;
a first passive device structure disposed between the package substrate and the redistribution structure, the first passive device structure comprising:
a first substrate;
a first passive device disposed on the first substrate;
a first through via extending through the first substrate and electrically connected to the first passive device; and
a second through via extending through the first substrate, wherein the first through via and the second through via are electrically connected to the redistribution structure and to the first semiconductor device;

a second passive device structure disposed between the package substrate and the redistribution structure, the second passive device structure comprising:
a second substrate;
a second passive device disposed on the second substrate;
a third through via extending through the second substrate and electrically connected to the second passive device; and
a fourth through via extending through the second substrate, wherein the third through via and the fourth through via are electrically connected to the redistribution structure and to the second semiconductor device;

a molding compound surrounding each of the first passive device structure, the second passive device structure, the via, and the third semiconductor device; and wherein an integrated passive device coupled to the redistribution structure opposite the package substrate.

10. The device of claim 9 , wherein the first through via and the second through via are connected to the same terminal of the first passive device.

11. The device of claim 9 , wherein the first through via is configured to transmit a supply voltage to the first semiconductor device, and the second through via is configured to transmit an electrical signal to the first semiconductor device.

12. The device of claim 9 , wherein the first passive device of the first passive device structure is a capacitor.

13. The device of claim 9 , further comprising at least one redistribution layer disposed between the via and the package substrate.

14. A package structure comprising:
a set of vias on and electrically connected to a redistribution structure;
a first die on and electrically connected to the redistribution structure, the first die being spaced apart from the set of vias;
a first interconnect structure on and electrically connected to the redistribution structure, the first interconnect structure being spaced apart from the first die and the set of vias, the first interconnect structure comprising:
a substrate;
a first conductive element and a second conductive element extending from one side of the substrate to a second side of the substrate;
a metallization layer disposed over and electrically connected to the first conductive element and the second conductive element; and
an integrated passive device, wherein the integrated passive device is electrically connected to the first conductive element and the second conductive element through the metallization layer;

an encapsulant covering and in physical contact with the set of vias, the first die, and the first interconnect structure in an encapsulant;
a top package over the set of vias, the first die, and the first interconnect structure, wherein the top package comprises a second die, and wherein the second die is electrically connected to the integrated passive device; and wherein another integrated passive device is coupled to the redistribution structure opposite the top package.

15. The package structure of claim 14 , further comprising a second interconnect structure on and electrically connected to the redistribution structure, the second interconnect structure being spaced apart from the first interconnect structure, the first die, and the set of vias.

16. The package structure of claim 14 , wherein the integrated passive device comprises a trench capacitor.

17. The package structure of claim 14 , wherein the integrated passive device is at a first side of the first interconnect structure that faces the top package.

18. The package structure of claim 14 , wherein the top package is separated from the first interconnect structure by an underfill material.

19. The package structure of claim 14 , wherein the first interconnect structure is physically free of active devices.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Chuei-Tang
• Tsai Chung-Hao
• Yu Chen-Hua

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title