Power module

Patent metadata

Field	Value
Publication number	US-2024421106-A1
Application number	US-202318389512-A
Country	US
Kind code	A1
Filing date	Nov 14, 2023
Priority date	Jun 19, 2023
Publication date	Dec 19, 2024
Grant date	—

Abstract

Introduced is a power module including a first substrate and a second substrate, a semiconductor chip, and a via spacer electrically connecting the first substrate and the second substrate, wherein the via spacer includes a first portion electrically connected to the first substrate, a second portion electrically connected to the second substrate, and a resistor portion including a resistance value greater than resistance values of the first portion and the second portion and arranged between the first portion and the second portion.

First claim

What is claimed is:

1 . A power module comprising:
a first substrate and a second substrate, each of which includes an insulating layer and a metal layer disposed on one surface of the insulating layer, wherein the metal layers are arranged and spaced from each other to face each other in a first direction; a semiconductor chip disposed between the first substrate and the second substrate in the first direction; and a via spacer extending in the first direction, electrically connecting the first substrate and the second substrate, between the first substrate and the second substrate and separated from the semiconductor chip with a predetermined distance in a second direction crossing the first direction, wherein the via spacer includes:
a first portion electrically connected to the first substrate;
a second portion electrically connected to the second substrate; and
a resistor portion including a resistance value greater than resistance values of the first portion and the second portion and arranged between the first portion and the second portion in the first direction.

2 . The power module of claim 1 , wherein the first portion and the second portion extend in a same length in the first direction, and the resistor portion is disposed at a center portion of the via spacer.

3 . The power module of claim 1 , wherein the resistor portion extends in a same length as the first portion and the second portion in the second direction.

4 . The power module of claim 1 , wherein potentials of the first portion and the second portion are transferred to at least one of the first substrate and the second substrate.

5 . The power module of claim 4 , wherein at least one of the first substrate and the second substrate includes a plurality of patterns individually formed to receive the potentials.

6 . The power module of claim 5 , wherein the first portion and the second portion are each connected to the plurality of patterns through a wire.

7 . The power module of claim 5 , wherein the plurality of patterns are connected to a signal lead transferring the received potentials to an outside of the power module.

8 . The power module of claim 1 , wherein the via spacer receives a first current passed through the semiconductor chip through one of the first substrate and the second substrate and transfers the received first current to another of the first substrate and the second substrate.

9 . The power module of claim 8 , wherein the resistor portion receives a second current for sensing the first current, separately from the first current.

10 . The power module of claim 9 , wherein the second current includes a current value less than a current of the first current.

11 . The power module of claim 1 , further including a chip spacer connecting a first surface of the semiconductor chip to one of the first substrate and the second substrate and a second surface of the semiconductor chip is connected to a remaining one of the first substrate and the second substrate.

12 . The power module of claim 11 , wherein the chip spacer is connected to the first surface of the semiconductor chip and the one of the first substrate and the second substrate by an adhesive and the second surface of the semiconductor chip is connected to the remaining one of the first substrate and the second substrate by the adhesive.

13 . The power module of claim 1 , wherein the first substrate and the second substrate includes additional metal layers arranged on opposite sides of the insulating layers, facing an outside of the power module.

Assignees

• Hyundai Motor Co Ltd
• Kia Corp

Inventors

• Yang Jin Myeong
• Park Sung Won
• Do Han Jin

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W44/401 Primary

  Resistive arrangements (H10W44/20, H10W42/80 take precedence) · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/658

  for devices provided for in groups H10D8/00 - H10D48/00 · CPC title