Stacked semiconductor device

Patent metadata

Field	Value
Publication number	US-2016233195-A1
Application number	US-201614991465-A
Country	US
Kind code	A1
Filing date	Jan 8, 2016
Priority date	Feb 5, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

A stacked semiconductor device includes: a plurality of stacked integrated-circuit chips that are to be mounted onto a substrate and including at least one power-supply target chip; a decoupling through-electrode transmission line including a decoupling power-supply-side through-electrode wiring line coupled to a power-supply terminal of the at least one power-supply target chip and a decoupling ground-side through-electrode wiring line coupled to a ground terminal of the at least one power-supply target chip; a resistor and a capacitor provided one of the a plurality of integrated-circuit chips that is located at a termination of the decoupling through-electrode transmission line, the resistor having an impedance substantially equal to a characteristic impedance of the decoupling through-electrode transmission line, wherein the resistor and the capacitor are coupled in series.

First claim

What is claimed is:

1 . A stacked semiconductor device comprising:
a plurality of stacked integrated-circuit chips that are to be mounted onto a substrate and including at least one power-supply target chip; a decoupling through-electrode transmission line including a decoupling power-supply-side through-electrode wiring line coupled to a power-supply terminal of the at least one power-supply target chip and a decoupling ground-side through-electrode wiring line coupled to a ground terminal of the at least one power-supply target chip; a resistor and a capacitor provided one of the a plurality of integrated-circuit chips that is located at a termination of the decoupling through-electrode transmission line, the resistor having an impedance substantially equal to a characteristic impedance of the decoupling through-electrode transmission line, wherein the resistor and the capacitor are coupled in series.

2 . The stacked semiconductor device according to claim 1 ,
wherein a first end of the resistor is coupled to one of the power-supply terminal and the ground terminal, a second end of the resistor is coupled to a first end of the capacitor, and a second end of the capacitor is coupled to the other of the power-supply terminal and the ground terminal.

3 . The stacked semiconductor device according to claim 1 ,
wherein a plurality of the decoupling through-electrode transmission lines each corresponding the decoupling through-electrode transmission line are arranged.

4 . The stacked semiconductor device according to claim 1 ,
wherein the power-supply target chip includes a power-supply-side wiring line coupled to the power-supply terminal, a ground-side wiring line coupled to the ground terminal, and a terminal-side transmission line having a characteristic impedance substantially equal to the characteristic impedance of the decoupling through-electrode transmission line, and wherein the power-supply terminal and the ground terminal are coupled to the decoupling through-electrode transmission line through the terminal-side transmission line.

5 . The stacked semiconductor device according to claim 1 ,
wherein the decoupling ground-side through-electrode wiring line is provided around the decoupling power-supply-side through-electrode wiring line.

6 . The stacked semiconductor device according to claim 1 ,
wherein the decoupling through-electrode transmission line extends toward a portion above the power-supply target chip, and wherein the resistor and the capacitor are provided in a highest integrated-circuit chip of the plurality of integrated-circuit chips.

7 . The stacked semiconductor device according to claim 1 ,
wherein the decoupling through-electrode transmission line extends toward a portion below the power-supply target chip, and wherein the resistor and the capacitor are provided in a lowest integrated-circuit chip of the plurality of integrated-circuit chips.

8 . The stacked semiconductor device according to claim 7 ,
wherein the lowest integrated-circuit chip includes a power-supply wiring line, a ground wiring line, and a low-pass filter, and wherein the decoupling power-supply-side through-electrode wiring line and the decoupling ground-side through-electrode wiring line are coupled, at the termination of the decoupling through-electrode transmission line, to the power-supply wiring line and the ground wiring line, respectively, through the low-pass filter.

9 . The stacked semiconductor device according to claim 1 , wherein the decoupling through-electrode transmission line includes an upper decoupling through-electrode transmission line extending toward a portion above the power-supply target chip and a lower decoupling through-electrode transmission line extending toward a portion below the power-supply target chip,
the resistor and the capacitor includes an upper resistor and a upper capacitor provided in a highest integrated-circuit chip of the plurality of integrated-circuit chips and coupled to a termination of the upper decoupling through-electrode transmission line and a lower resistor and a lower capacitor provided in a lowest integrated-circuit chip of the plurality of integrated-circuit chips and coupled to a termination of the lower decoupling through-electrode transmission line, the upper resistor having an impedance substantially equal to a characteristic impedance of the upper decoupling through-electrode transmission line, and the lower resistor having an impedance substantially equal to the characteristic impedance of the lower decoupling through-electrode transmission line.

10 . The stacked semiconductor device according to claim 9 ,
wherein the lowest integrated-circuit chip includes a power-supply wiring line, a ground wiring line, and a low-pass filter, and wherein the decoupling power-supply-side through-electrode wiring line and the decoupling ground-side through-electrode wiring line, at the termination of the lower decoupling through-electrode transmission line, to the power-supply wiring line and the ground wiring line, respectively, through the low-pass filter.

11 . The stacked semiconductor device according to claim 1 ,
wherein one of the a plurality of integrated-circuit chips includes a termination-side transmission line having a characteristic impedance substantially equal to the characteristic impedance of the decoupling through-electrode transmission line, and wherein the resistor and the capacitor are coupled to the termination of the decoupling through-electrode transmission line through the termination-side transmission line.

12 . The stacked semiconductor device according to claim 1 , further comprising:
an adjustment capacitor, coupled between the decoupling power-supply-side through-electrode wiring line and the decoupling ground-side through-electrode wiring line, configured to adjust the characteristic impedance of the decoupling through-electrode transmission line.

Assignees

• Fujitsu Ltd

Inventors

• Nagai Toshiaki

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/01

  Manufacture or treatment · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title