THROUGH-SILICON VIA (TSV) CRACK SENSORS FOR DETECTING TSV CRACKS IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs), AND RELATED METHODS AND SYSTEMS

Patent metadata

Field	Value
Publication number	US-2016258996-A1
Application number	US-201514639511-A
Country	US
Kind code	A1
Filing date	Mar 5, 2015
Priority date	Mar 5, 2015
Publication date	Sep 8, 2016
Grant date	—

Abstract

Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems are disclosed. In one aspect, a TSV crack sensor circuit is provided in which doped rings for a plurality of TSVs are interconnected in parallel such that all interconnected TSV doped rings may be tested at the same time by providing a single current into the contacts of the interconnected doped rings. In another aspect, a TSV crack sensor circuit is provided including one or more redundant TSVs. Each doped ring for a corresponding TSV is tested independently, and a defective TSV may be replaced with a spare TSV whose doped ring is not detected to be cracked. This circuit allows for correction of a compromised 3DIC by replacing possibly compromised TSVs with spare TSVs.

First claim

What is claimed is:

1 . A three-dimensional integrated circuit (3DIC) comprising:
a plurality of through-silicon vias (TSVs) configured to interconnect at least two layers of the 3DIC; a plurality of TSV crack sensors, each TSV crack sensor among the plurality of TSV crack sensors corresponding to a TSV of the plurality of TSVs, each TSV crack sensor, comprising:
a doped ring disposed around the corresponding TSV;
a first contact disposed on a first location of the doped ring; and
a second contact disposed on a second location of the doped ring such that doped ring resistance comprising a parallel resistance of a first resistance and a second resistance is provided in the doped ring between the first contact and the second contact;
a first interconnection coupled to the first contact of each TSV crack sensor among the plurality of TSV crack sensors and coupled to a first conductor; and a second interconnection coupled to the second contact of each TSV crack sensor among the plurality of TSV crack sensors and coupled to a second conductor.

2 . The 3DIC of claim 1 , configured to receive a current across the first conductor and the second conductor to generate a voltage (V) between the first interconnection and the second interconnection based on the doped ring resistance of each TSV crack sensor of the plurality of TSV crack sensors.

3 . The 3DIC of claim 2 , wherein each TSV crack sensor is configured to set one of the first resistance and the second resistance as an open circuit when a crack extends radially from the corresponding TSV through the corresponding doped ring.

4 . The 3DIC of claim 3 , wherein the voltage (V) between the first interconnection and the second interconnection is:

V
=

R

2

N

-
X


I

wherein R is a value of the first resistance and of the second resistance, N is a number of TSV crack sensors in the plurality of TSV crack sensors, and X is a number of resistances from a plurality of first resistances and a plurality of second resistances set as the open circuit when the crack extends radially from the corresponding TSV through the corresponding doped ring.

5 . The 3DIC of claim 2 , further comprising:
a first external connector coupled to the first interconnection and configured to receive the current from an external source and to provide the voltage (V) to an external voltage sensor.

6 . The 3DIC of claim 5 , further comprising:
a sensor coupled to the first interconnection and configured to measure the generated voltage.

7 . The 3DIC of claim 2 , further comprising:
a controller coupled to the first interconnection and configured to provide the current.

8 . The 3DIC of claim 7 , further comprising:
a sensor coupled to the first interconnection and configured to measure the voltage (V).

9 . The 3DIC of claim 2 , wherein a first location of the corresponding doped ring is at a boundary of the corresponding doped ring and a second location of the corresponding doped ring is at another boundary of the corresponding doped ring such that the first location is symmetrically opposite to the second location relative to the corresponding TSV.

10 . The 3DIC of claim 1 , wherein each doped ring is an n+ type doped ring and is disposed on a p− substrate of a layer of the at least two layers.

11 . The 3DIC of claim 1 , wherein each doped ring is a p− type doped ring and is disposed on an n+ substrate of a layer of the at least two layers.

12 . The 3DIC of claim 1 , wherein each TSV of the plurality of TSVs comprises:
a conductive material configured to interconnect the at least two layers of the 3DIC; and a dielectric liner disposed around the conductive material, configured to electrically isolate the conductive material from a substrate of the at least two layers.

13 . The 3DIC of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; and a portable digital video player.

14 . A method for testing a three-dimensional integrated circuit (3DIC) for through-silicon via (TSV) cracks, comprising:
providing a current to a first interconnection point of a network of parallel TSV crack sensors; measuring a voltage across the network of parallel TSV crack sensors based on the current; comparing the measured voltage to a nominal voltage; providing an indication that the 3DIC is defective if the measured voltage is higher than the nominal voltage; and providing an indication that the 3DIC is not defective if the measured voltage is substantially equal to the nominal voltage.

15 . A through-silicon via (TSV) redundant crack sensor circuit for a three-dimensional integrated circuit (3DIC), comprising:
a TSV pair configured to interconnect at least two layers of the 3DIC; a TSV crack sensor pair, each TSV crack sensor of the TSV crack sensor pair corresponding to a TSV of the TSV pair, each TSV crack sensor comprising:
a doped ring disposed around the corresponding TSV;
a first contact disposed on a first location of the doped ring; and
a second contact disposed on a second location of the doped ring such that a first resistance and a second resistance are provided in the doped ring between the first contact and the second contact; and
a controller corresponding to the TSV pair, the controller coupled to each TSV crack sensor of the TSV crack sensor pair, the controller configured to select the TSV from the corresponding TSV pair based on sensor information from each TSV crack sensor of the corresponding TSV crack sensor pair.

16 . The TSV redundant crack sensor circuit of claim 15 , wherein the controller is configured to provide a current across the corresponding first contact and the second contact of each TSV of the corresponding TSV pair and to select the TSV of the corresponding TSV pair based on a resistance across each TSV of the corresponding TSV pair.

17 . The TSV redundant crack sensor circuit of claim 16 , wherein each TSV crack sensor of the TSV crack sensor pair is configured to set one of the first resistance and the second resistance as an open circuit when a crack extends radially from the corresponding TSV through the corresponding doped ring.

18 . The TSV redundant crack sensor circuit of claim 17 , further comprising:
a first external connector coupled to the controller and configured to provide, to an external device, an indication of the status of the TSV redundant crack sensor circuit.

19 . The TSV redundant crack sensor circuit of claim 17 , further comprising:
a sense amplifier pair, each sense amplifier of the sense amplifier pair corresponding to the TSV crack sensor of the TSV crack sensor pair, each s

Assignees

• Qualcomm Inc

Inventors

• Lim Sung Kyu
• Radojcic Ratibor
• Du Yang

Classifications

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W44/401

  Resistive arrangements (H10W44/20, H10W42/80 take precedence) · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title