Low temperature fabrication of lateral thin film varistor

Patent metadata

Field	Value
Publication number	US-9356089-B1
Application number	US-201514632074-A
Country	US
Kind code	B1
Filing date	Feb 26, 2015
Priority date	Feb 26, 2015
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

First claim

What is claimed is:

1. A lateral thin film varistor comprising:
a continuous layer comprising alternating regions of a first metal oxide layer and a second metal oxide layer located between, and in contact with, two laterally spaced electrodes.

2. The lateral thin film varistor of claim 1 , wherein the first metal oxide layer comprises zinc oxide.

3. The lateral thin film varistor of claim 1 , wherein the second metal oxide layer comprises bismuth oxide.

Assignees

• IBM

Inventors

• Gambino Jeffrey P
• Graf Richard S
• Mandal Sudeep

Classifications

• H10P14/6939

  characterised by the metal · CPC title

• H10P14/6329

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10P14/662

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W44/401

  Resistive arrangements (H10W44/20, H10W42/80 take precedence) · CPC title