Low temperature fabrication of lateral thin film varistor

Patent metadata

Field	Value
Publication number	US-2016254344-A1
Application number	US-201615149652-A
Country	US
Kind code	A1
Filing date	May 9, 2016
Priority date	Feb 26, 2015
Publication date	Sep 1, 2016
Grant date	—

Abstract

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

First claim

What is claimed is:

1 . A lateral thin film varistor device, comprising:
a substrate; a first dielectric layer on the substrate; a second dielectric layer on the first dielectric layer; a continuous, varistor layer on the second dielectric layer and comprising alternating regions of a first metal oxide layer and a second metal oxide layer located between, and in contact with, two laterally spaced electrodes; and a third dielectric layer on said continuous, varistor layer.

2 . The lateral thin film varistor device according to claim 1 , wherein the third dielectric layer is directly on said continuous, varistor layer.

3 . The lateral thin film varistor device according to claim 1 , further comprising:
an isolation layer between the second and third dielectric layers, and wherein: the continuous, varistor is positioned in said isolation layer; and the third dielectric layer is directly on the isolation layer and the continuous, varistor.

4 . The lateral thin film varistor device according to claim 1 , further comprising a capping layer interposed between the first and second dielectric layers.

5 . A lateral thin film varistor device according to claim 1 , further comprising a top capping layer on the third dielectric layer.

6 . A lateral thin film varistor device according to claim 1 , further comprising a plurality of electrically conductive vias in the third dielectric layer and in electrical contact with the two electrodes.

7 . A lateral thin film varistor device according to claim 1 , wherein the third dielectric layer laterally extends past the alternating regions of the first and second metal oxide layers.

8 . A lateral thin film varistor device according to claim 1 , further comprising an electrically conductive interconnect extending through the third dielectric layer.

9 . A lateral thin film varistor device according to claim 1 , further comprising a plurality of electrically conductive lines in the third dielectric layer.

10 . A lateral thin film varistor device according to claim 1 , wherein the third dielectric layer laterally extends over the two electrodes.

11 . A method of forming a lateral thin film varistor device, comprising:
forming a continuous, varistor layer comprising alternating regions of a first metal oxide layer and a second metal oxide layer between two laterally spaced electrodes using a sputtering process followed by an annealing process, including forming the continuous, varistor layer above separate first and second dielectric layers; and forming a third dielectric layer on said continuous, varistor layer.

12 . The method according to claim 11 , wherein the forming a third dielectric layer includes forming the third dielectric layer directly on the continuous, varistor layer.

13 . The method according to claim 12 , further comprising:
forming an isolation layer between the second and third dielectric layers, and wherein: the forming a continuous varistor layer includes forming the continuous, varistor layer in said isolation layer.

14 . The method according to claim 11 , further comprising:
forming a capping layer above the first dielectric layer; and wherein: the second dielectric layer is on said capping layer.

15 . The method according to claim 11 , further comprising forming a top cap layer on the third dielectric layer.

16 . A lateral thin film varistor device, comprising:
a substrate; a first dielectric layer on the substrate; a capping layer on the first dielectric layer a second dielectric layer on the first dielectric layer; an isolation layer on the second dielectric layer; a continuous, varistor layer in the isolation layer, above the second dielectric layer and comprising alternating regions of a first metal oxide layer and a second metal oxide layer located between, and in contact with, two laterally spaced electrodes; and a third dielectric layer on said continuous, varistor layer.

17 . The lateral thin film varistor device according to claim 16 , wherein the third dielectric layer is directly on said continuous, varistor layer.

18 . The lateral thin film varistor device according to claim 16 , wherein the third dielectric layer is directly on said isolation layer.

19 . The lateral thin film varistor device according to claim 16 , wherein the laterally spaced electrodes directly contact regions of the first metal oxide layer.

20 . The lateral thin film varistor device according to claim 16 , wherein the third dielectric layer laterally extends past the alternating regions of the first and second metal oxide layers and laterally over the two electrodes.

Assignees

• IBM

Inventors

• Gambino Jeffrey P
• Graf Richard S
• Mandal Sudeep

Classifications

• H10P14/6939

  characterised by the metal · CPC title

• H10P14/6329

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10P14/662

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W44/401

  Resistive arrangements (H10W44/20, H10W42/80 take precedence) · CPC title