Semiconductor structure, dicing method thereof, and memory

Patent metadata

Field	Value
Publication number	US-2024379578-A1
Application number	US-202318381030-A
Country	US
Kind code	A1
Filing date	Oct 17, 2023
Priority date	May 12, 2023
Publication date	Nov 14, 2024
Grant date	—

Abstract

According to one aspect of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a first wafer. The first wafer may include a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer. A pointing direction of the first mark may be the same as an extending direction of the first dicing lane. A cleavage plane of the first wafer may be parallel to the pointing direction of the first mark. The pointing direction of the first mark may be an extending direction of a line of symmetry of the first wafer. The semiconductor structure may include a second wafer. The second wafer and the first wafer may be disposed in a stack. The second wafer may be a plurality of memory array chips.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a first wafer, comprising:
a plurality of first peripheral circuit chips;
a first dicing lane between the first peripheral circuit chips; and
a first mark at an edge of the first wafer,
wherein a pointing direction of the first mark is the same as an extending direction of the first dicing lane, a cleavage plane of the first wafer is parallel to the pointing direction of the first mark, and the pointing direction of the first mark is an extending direction of a line of symmetry of the first wafer; and

a second wafer,
wherein the second wafer and the first wafer are disposed in a stack, and the second wafer comprises a plurality of memory array chips.

2 . The semiconductor structure of claim 1 , further comprising:
a third wafer, comprising: a plurality of second peripheral circuit chips; a second dicing lane between the second peripheral circuit chips; and a second mark at an edge of the third wafer,
wherein an extending direction of the second dicing lane is the same as the extending direction of the first dicing lane.

3 . The semiconductor structure of claim 2 , wherein:
an included angle between a pointing direction of the second mark and the extending direction of the second dicing lane is a, 0°<a<90°, characteristic sizes of devices in the second peripheral circuit chips are smaller than characteristic sizes of devices in the first peripheral circuit chips, and the pointing direction of the second mark is an extending direction of a line of symmetry of the third wafer.

4 . The semiconductor structure of claim 2 , wherein:
a pointing direction of the second mark is the same as the extending direction of the second dicing lane, a cleavage plane of the third wafer is parallel to the pointing direction of the second mark, characteristic sizes of devices in the first peripheral circuit chips are the same as characteristic sizes of devices in the second peripheral circuit chips, and the pointing direction of the second mark is an extending direction of a line of symmetry of the third wafer.

5 . The semiconductor structure of claim 2 , wherein the third wafer is located between the first wafer and the second wafer.

6 . The semiconductor structure of claim 2 , wherein the second wafer is located between the first wafer and the third wafer.

7 . The semiconductor structure of claim 1 , wherein the memory array chips comprise three-dimensional NAND memory array chips.

8 . A method of dicing a semiconductor structure, comprising:
providing a semiconductor structure to be diced,
wherein the semiconductor structure to be diced comprises a first wafer and a second wafer,
wherein the first wafer comprises a plurality of first peripheral circuit chips, a first dicing lane between the first peripheral circuit chips, and a first mark at an edge of the first wafer, a pointing direction of the first mark is the same as an extending direction of the first dicing lane, and a cleavage plane of the first wafer is parallel to the pointing direction of the first mark,
wherein the second wafer and the first wafer are disposed in a stack, and the second wafer comprises a plurality of memory array chips, and
wherein the pointing direction of the first mark is an extending direction of a line of symmetry of the first wafer;
dicing the first dicing lane from a side of the first wafer away from the second wafer; and stretching the semiconductor structure to be diced, such that the cleavage plane of the first wafer extends to the second wafer.

9 . The method of claim 8 , wherein the dicing the first dicing lane of the first wafer from the side of the first wafer away from the second wafer comprises:
dicing the first dicing lane of the first wafer from the side of the first wafer away from the second wafer by using a laser dicing process.

10 . The method of claim 8 , wherein the semiconductor structure further comprises:
a third wafer,
wherein the third wafer comprises a plurality of second peripheral circuit chips, a second dicing lane between the second peripheral circuit chips, and a second mark at an edge of the third wafer, and
wherein an extending direction of the second dicing lane is the same as the extending direction of the first dicing lane.

11 . The method of claim 10 , wherein:
an included angle between a pointing direction of the second mark and the extending direction of the second dicing lane is a, 0°<a<90°, and characteristic sizes of devices in the second peripheral circuit chips are smaller than characteristic sizes of devices in the first peripheral circuit chips, the pointing direction of the second mark is an extending direction of a line of symmetry of the third wafer, and the stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer comprises:
stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer and the third wafer.

12 . The method of claim 10 , wherein:
a pointing direction of the second mark is the same as the extending direction of the second dicing lane, a cleavage plane of the third wafer is parallel to the pointing direction of the second mark, and characteristic sizes of devices in the first peripheral circuit chips are the same as characteristic sizes of devices in the second peripheral circuit chips, the pointing direction of the second mark is an extending direction of a line of symmetry of the third wafer, the second wafer is located between the first wafer and the third wafer, and the method further comprises:
dicing the second dicing lane from a side of the third wafer away from the second wafer while dicing the first dicing lane from the side of the first wafer away from the second wafer; and
stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer comprises:
stretching the semiconductor structure to be diced, such that the cleavage plane of the first wafer and the cleavage plane of the third wafer extend to the second wafer.

13 . The method of claim 10 , wherein:
a pointing direction of the second mark is the same as the extending direction of the second dicing lane, a cleavage plane of the third wafer is parallel to the pointing direction of the second mark, and characteristic sizes of devices in the first peripheral circuit chips are the same as characteristic sizes of devices in the second peripheral circuit chips, the pointing direction of the second mark is an extending direction of a line of symmetry of the third wafer, the third wafer is located between the first wafer and the second wafer, and the dicing the first dicing lane from the side of the first wafer away from the second wafer comprises:
dicing the first dicing lane and the second dicing lane from the side of the first wafer away from the second wafer; and
stretching the semiconductor structure to be diced such that the cleavage plane of the first wafer extends to the second wafer comprises:
stretching the semiconductor structure to be diced, such that the cleavage plane of the first wafer and the cleavage plane of the third wafer extend to the second wafer.

14 . The method of claim 8 , wherein the stretching the semiconductor structure to be diced comprises:
stretching the semiconductor structure to be diced along a direction perpendicular to the cleavage plane of the first wafer.

15 . The method of claim 8 , wherein the providing the semiconductor struc

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Fan Dongyu
• Gao Tingting
• Xie Wei
• Lv Zhong
• Xia Zhiliang
• Huo Zongliang

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P34/42

  with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

• H10W46/503

  Located in scribe lines · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title