Semiconductor die, semiconductor package and substrate dicing method
US-2024421000-A1 · Dec 19, 2024 · US
Electricity
Electricity · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10W46/503 |
| Official title | — |
| Display label | Electricity (mapped technology topic) |
| Total patents | 1,369 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 104 |
| 2016 | 108 |
| 2017 | 173 |
| 2018 | 149 |
| 2019 | 117 |
| 2020 | 156 |
| 2021 | 126 |
| 2022 | 104 |
| 2023 | 102 |
| 2024 | 106 |
| 2025 | 103 |
| 2026 | 21 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Methods and Apparatus Using Front-to-Back Alignment Mark and Placement for Narrow Wafer Scribe Lines
US-2015380358-A1 · Dec 31, 2015 · US
Semiconductor devices and methods of manufacture thereof
US-9209140-B2 · Dec 8, 2015 · US
Semiconductor apparatus and substrate
US-9190363-B2 · Nov 17, 2015 · US
Alignment mark
US-9188883-B2 · Nov 17, 2015 · US
Substrate dividing method
US-2015311119-A1 · Oct 29, 2015 · US
Dicing Structures for Semiconductor Substrates and Methods of Fabrication Thereof
US-2015311162-A1 · Oct 29, 2015 · US
Method of die singulation using laser ablation and induction of internal defects with a laser
US-9165832-B1 · Oct 20, 2015 · US
Chip package comprising alignment mark and method for forming the same
US-9165890-B2 · Oct 20, 2015 · US
Dicing processes for thin wafers with bumps on wafer backside
US-2015279739-A1 · Oct 1, 2015 · US
Substrate dividing method
US-9142458-B2 · Sep 22, 2015 · US
Semiconductor Workpiece Having a Semiconductor Substrate with at Least Two Chip Areas
US-2015262942-A1 · Sep 17, 2015 · US
Multiple-patterning overlay decoupling method
US-9134627-B2 · Sep 15, 2015 · US
Chip identification pattern and method of forming
US-9136222-B2 · Sep 15, 2015 · US
Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding
US-2015255417-A1 · Sep 10, 2015 · US
Method for Forming Alignment Marks and Structure of Same
US-2015255400-A1 · Sep 10, 2015 · US
Method of manufacturing a semiconductor device and semiconductor integrated circuit wafer
US-2015255373-A1 · Sep 10, 2015 · US
Semiconductor device
US-9123571-B2 · Sep 1, 2015 · US
Mark formation method and device manufacturing method
US-2015234279-A1 · Aug 20, 2015 · US
Semiconductor device manufacturing method and semiconductor device
US-2015235973-A1 · Aug 20, 2015 · US
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10W46/503?
- CPC H10W46/503 is the Cooperative Patent Classification code for “Electricity.”
- How many patents are filed under CPC H10W46/503 (Electricity)?
- Our database includes 1,369 publications tagged with this CPC code.
- Is patent activity under CPC H10W46/503 growing?
- Publication counts under this code: 106 in 2024 vs 103 in 2025 (latest complete years).