Method of fabricating tunneling transistor

Patent metadata

Field	Value
Publication number	US-2019214463-A1
Application number	US-201916354126-A
Country	US
Kind code	A1
Filing date	Mar 14, 2019
Priority date	Jul 18, 2016
Publication date	Jul 11, 2019
Grant date	—

Abstract

A tunneling transistor and a method of fabricating the same, the tunneling transistor includes a fin shaped structure, a source structure and a drain structure, and a gate structure. The fin shaped structure is disposed in a substrate, and the source structure and the drain structure are disposed the fin shaped structure, wherein an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials. A channel region is disposed in the fin shaped structure between the source structure and the drain structure and the gate structure is disposed on the channel region. That is, a hetero tunneling junction is vertically formed between the channel region and the source structure, and between the channel region and the drain structure in the fin shaped structure.

First claim

What is claimed is:

1 . A method of forming a tunneling transistor, comprising:
forming a fin shaped structure in a substrate; forming a gate structure across the fin shaped structure; forming two recesses at two sides of the gate structure in the fin shaped structure, wherein each of the recesses comprises a sidewall having an edge inclined toward the gate structure; forming a source structure in one of the recesses; and forming a drain structure in another one of the recesses, an entirety of the source structure and an entirety of the drain structure being of complementary conductivity types with respect to one another and having different materials.

2 . The method of forming a tunneling transistor according to claim 1 , wherein the gate structure comprises a spacer and the edge is formed under the spacer in a projecting direction.

3 . The method of forming a tunneling transistor according to claim 1 , wherein the recesses are formed through a dry etching process.

4 . The method of forming a tunneling transistor according to claim 1 , wherein the source structure and the drain structure are asymmetric in shape.

5 . The method of forming a tunneling transistor according to claim 1 , further comprising:
performing an ion implanting process before the source structure and the drain structure are formed, to form a doped region on surfaces of the sidewall.

6 . The method of forming a tunneling transistor according to claim 1 , further comprising:
performing an in situ doping process while the source structure and the drain structure are formed.

7 . The method of forming a tunneling transistor according to claim 1 , wherein the forming of the recesses comprising:
forming a first recess at one side of the gate structure in the fin shaped structure; and forming a second recess at another side of the gate structure in the fin shaped structure, wherein the source structure is formed in the first recess before the second recess is formed.

8 . The method of forming a tunneling transistor according to claim 1 , wherein the source structure or the drain structure comprises SiP.

9 . The method of forming a tunneling transistor according to claim 1 , wherein the source structure comprises SiGe with a concentration of Ge therein being gradually decreased along a direction away from a channel region, and the drain structure comprises SiP with a concentration of C being gradually decreased along the direction away from the channel region.

10 . The method of forming a tunneling transistor according to claim 1 , wherein the drain structure comprises SiGe with a concentration of Ge therein being gradually decreased along a direction away from the channel region, and the source structure comprises SiP with a concentration of C being gradually decreased along the direction away from the channel region.

Assignees

• United Microelectronics Corp

Inventors

• Chen Cheng-Guo
• Wu Kun-Yuan
• Chen Tai-You
• Ho Chiu-Sheng
• Yang Po-Kang
• Lo Ta-Kang

Classifications

• H01L29/267

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L29/66636

  Electricity · mapped topic

• H01L29/0847 Primary

  Electricity · mapped topic

• H01L29/7391

  Electricity · mapped topic