Tunneling field effect transistor (tfet) having a semiconductor fin structure

Patent metadata

Field	Value
Publication number	US-2016322479-A1
Application number	US-201514698921-A
Country	US
Kind code	A1
Filing date	Apr 29, 2015
Priority date	Apr 29, 2015
Publication date	Nov 3, 2016
Grant date	—

Abstract

A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.

First claim

What is claimed is:

1 . A tunneling field effect transistor, comprising:
a support substrate; a fin of semiconductor material including a source region, a drain region and a channel region between the source region and drain region; a gate electrode straddling over the fin at said channel region; sidewall spacers on each side of the gate electrode; an epitaxial germanium content source region grown from the source region of said fin and doped with a first conductivity type; and an epitaxial silicon content drain region grown from the drain region of said fin and doped with a second conductivity type.

2 . The tunneling field effect transistor of claim 1 , wherein said source region is doped with the first conductivity type and the drain region is doped with the second conductivity type.

3 . The tunneling field effect transistor of claim 2 , wherein the source and channel regions of the fin of semiconductor material have a first thickness and wherein the drain region of the fin of semiconductor material has a second thickness less than the first thickness.

4 . The tunneling field effect transistor of claim 2 , wherein said fin of semiconductor material has a germanium content in excess of 80%.

5 . The tunneling field effect transistor of claim 4 , wherein said fin of semiconductor material is made of germanium.

6 . The tunneling field effect transistor of claim 4 , wherein said fin of semiconductor material is made of silicon-germanium.

7 . The tunneling field effect transistor of claim 2 , wherein said channel region is doped with the second conductivity type.

8 . The tunneling field effect transistor of claim 1 , wherein the channel region of the fin of semiconductor material has a first thickness and wherein the source and drain regions of the fin of semiconductor material have second thicknesses less than the first thickness.

9 . The tunneling field effect transistor of claim 1 , wherein said fin of semiconductor material is made of tensile strained silicon.

10 . The tunneling field effect transistor of claim 1 , wherein the gate electrode comprises: a work function metal and a ferroelectric material.

11 . The tunneling field effect transistor of claim 1 , wherein the gate electrode comprises: a work function metal and a metal fill.

12 . The tunneling field effect transistor of claim 1 , wherein said support substrate comprises a silicon on insulator substrate.

13 . The tunneling field effect transistor of claim 1 , wherein said support substrate comprises a bulk substrate.

14 . The tunneling field effect transistor of claim 1 , wherein the gate electrode further straddles over the fin of semiconductor material at a portion of the source region of said fin of semiconductor material.

15 . A method, comprising:
defining a fin of semiconductor material on a support substrate, said fin of semiconductor material including a source region, a drain region and a channel region between the source region and drain region; forming a gate stack straddling over the fin at said channel region; forming sidewall spacers on each side of the gate stack; epitaxially growing a germanium content source region from the source region of said fin, said germanium content source region doped with a first conductivity type; and epitaxially growing a silicon content drain region from the drain region of said fin, said silicon content drain region doped with a second conductivity type.

16 . The method of claim 15 , wherein defining a fin of semiconductor material comprises:
forming a layer of semiconductor material; doping the source region within said layer of semiconductor material with the first conductivity type; doping the drain region within said layer of semiconductor material with the second conductivity type; and patterning said layer of semiconductor material to define said fin.

17 . The method of claim 16 , further comprising reducing a thickness of the drain region of said fin of semiconductor material to be less than a thickness of the source and channel regions.

18 . The method of claim 16 , wherein forming the layer of semiconductor material comprises forming said layer with germanium content in excess of 80%.

19 . The method of claim 18 , wherein said layer of semiconductor material is made of germanium.

20 . The method of claim 18 , wherein said layer of semiconductor material is made of silicon-germanium.

21 . The method of claim 15 , wherein said channel region is doped with the second conductivity type.

22 . The method of claim 15 , wherein defining a fin of semiconductor material comprises:
forming a layer of tensile strained silicon semiconductor material; and patterning said layer of semiconductor material to define said fin.

23 . The method of claim 22 , further comprising reducing a thickness of the source and drain regions of said fin of semiconductor material to be less than a thickness of the channel region.

24 . The method of claim 15 , wherein forming the gate stack comprises: depositing a work function metal and depositing a ferroelectric material.

25 . The method of claim 15 , wherein forming the gate stack comprises;
providing a dummy gate stack; and replacing the dummy gate stack with a replacement metal gate comprising: a work function metal and a metal fill.

26 . The method of claim 15 , wherein said support substrate comprises a silicon on insulator substrate.

27 . The method of claim 15 , wherein said support substrate comprises a bulk substrate.

28 . The method of claim 15 , wherein forming the gate stack further comprises forming the gate stack to further straddle over the fin of semiconductor material at a portion of the source region of said fin of semiconductor material.

Assignees

• St Microelectronics Inc

Inventors

• Liu Qing
• Celik Salih Muhsin

Classifications

• H10D64/664

  the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H10D62/822 Primary

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D62/142

  Anode regions of thyristors or collector regions of gated bipolar-mode devices · CPC title