Low band gap semiconductor devices having reduced gate induced drain leakage (gidl) and their methods of fabrication

Patent metadata

Field	Value
Publication number	US-2019058053-A1
Application number	US-201515770628-A
Country	US
Kind code	A1
Filing date	Dec 21, 2015
Priority date	Dec 21, 2015
Publication date	Feb 21, 2019
Grant date	—

Abstract

Embodiments of the present invention are directed to low band gap channel semiconductor devices. In an example, a device includes a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap. A gate dielectric layer is on a surface of the first semiconductor material. A gate electrode is on the gate dielectric layer. A pair of source/drain regions is on opposite sides of the gate electrode. A channel is disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode. The pair of source/drain regions includes a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap. The second semiconductor material is between the first semiconductor material and the third semiconductor material, and the second band gap is greater than the first bandgap.

First claim

We claim:

1 . A device comprising:
a first semiconductor material formed above a substrate, the first semiconductor material having a first band gap; a gate dielectric layer on a surface of the first semiconductor material; a gate electrode on the gate dielectric layer; a pair of source/drain regions on opposite sides of the gate electrode; a channel disposed in the first semiconductor material between the pair of source/drain regions and beneath the gate electrode; and wherein the pair of source/drain regions comprises a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap, wherein the second semiconductor material is between the first semiconductor material and the third semiconductor material and wherein the second band gap is greater than the first bandgap.

2 . The device of claim 1 wherein the second bandgap is at least 150 meV greater than the first band gap.

3 . The device of claim 2 wherein the second bandgap is between 150 meV-500 meV greater than the first band gap.

4 . The device of claim 1 wherein the second bandgap is greater than the third band gap.

5 . The device of claim 1 wherein the channel region has a channel length, and wherein the second semiconductor has a thickness between 10-25% of the channel length.

6 . The device of claim 1 wherein the first semiconductor material is germanium.

7 . The device of claim 6 wherein the second semiconductor material is selected from the group consisting of a group III-V semiconductor and SiGe having a high Si content.

8 . The device of claim 7 wherein the second semiconductor is a graded SiGe semiconductor having a high Ge content near the channel and a lower Ge content near the third semiconductor material.

9 . The device of claim 1 wherein the second semiconductor material is formed on a surface of the first semiconductor material which is substantially coplanar with the surface on which gate dielectric layer is disposed.

10 . The device of claim 1 further comprising a pair of sidewall spacers formed along opposite sidewalls of the gate electrode, wherein the second semiconductor material is disposed on a surface of the first semiconductor material beneath the surface on which the gate dielectric layer is formed.

11 . The device of claim 10 wherein the second semiconductor material is located beneath the pair of sidewall spacers.

12 . A method of forming a device comprising:
forming a first semiconductor material above a substrate, the first semiconductor material having a first band gap; forming a gate dielectric on a surface of the first semiconductor material; forming a gate electrode on the gate dielectric layer; forming a second semiconductor material having a second band gap on the first semiconductor material on opposite sides of the gate electrode, the second band gap greater than the first bandgap; and forming a third semiconductor material having a third band gap on the second semiconductor material on opposite sides of the gate electrode.

13 . The method of claim 12 further comprising forming a pair of sidewall spacers along opposite sides of the gate electrode prior to forming the second semiconductor material and the third semiconductor material.

14 . The method of claim 13 further comprising etching a pair of recesses in the first semiconductor material on opposite sides of the gate electrode and the depositing the second semiconductor material and the third semiconductor material in the recesses.

15 . The method of claim 14 wherein the recesses extend beneath the pair of sidewall spacers.

16 . The method of claim 12 further comprising forming a sacrificial gate dielectric layer and a sacrificial gate electrode on the first semiconductor material prior to forming the second semiconductor material and the third semiconductor material; and
after forming the second semiconductor material and the third semiconductor material removing the sacrificial gate electrode and sacrificial gate dielectric layer and then forming the gate dielectric layer and gate electrode.

17 . A device comprising:
a fin comprising a first semiconductor material having a first band gap, the fin having a top and laterally opposite sidewalls; a gate dielectric layer on the top and laterally opposite sidewalls of the fin; a gate electrode on the gate dielectric layer on the top and laterally opposite sidewalls of the fin; a pair of source/drain region on opposite sides of the gate electrode, the pair of source/drain regions comprising a second semiconductor material having a second band gap, and a third semiconductor material having a third band gap, wherein the second semiconductor material is between the first semiconductor material and the third semiconductor material, and wherein the second band gap is greater than the first band gap.

18 . The device of claim 17 wherein the second band gap is at least 150 meV greater than the first band gap.

19 . The device of claim 17 wherein the second band gap is greater than the third band gap.

20 . The device of claim 17 wherein the second semiconductor is formed on the top and sidewalls of the fin on opposite sides of the gate electrode and wherein the third semiconductor is formed on the second semiconductor on the top and sidewalls of the fin.

21 . The device of claim 17 further comprising a pair of recesses formed on opposite side of the gate electrode, and wherein the first and second semiconductor materials are formed in the pair of recesses.

22 . The device of claim 21 further comprising a pair of sidewall spacers formed along laterally opposite sides of the gate electrode, wherein the pair of recesses extends beneath the laterally opposite sidewalls.

23 . The device of claim 17 wherein the first semiconductor material is germanium and the second semiconductor material is selected from the group consisting of a III-V semiconductor and SiGe.

24 . The device of claim 23 wherein the second semiconductor material is SiGe and wherein the SiGe is graded and has a larger Ge concentration near the first semiconductor material and a lower Ge concentration near the third semiconductor material.

Assignees

• Intel Corp

Inventors

• Dewey Gilbert
• Kavalieros Jack T
• Rachmady Willy
• Metz Matthew V
• Le Van H
• Kim Seiyon
• Chu-Kung Benjamin

Classifications

• H01L29/66583 Primary

  Electricity · mapped topic

• H01L29/512

  Electricity · mapped topic

• H01L29/0882

  Electricity · mapped topic

• H01L29/66689

  Electricity · mapped topic

• H01L29/0696

  Electricity · mapped topic