Tunnel field-effect transistor and method for producing same

Patent metadata

Field	Value
Publication number	US-10153343-B2
Application number	US-201515535437-A
Country	US
Kind code	B2
Filing date	Nov 4, 2015
Priority date	Dec 15, 2014
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A method for producing a tunnel field-effect transistor (TFET) having a source region, a channel region, and a drain region includes arranging an epitaxial layer on a silicon substrate; applying a gate arrangement having a gate electrode to the epitaxial layer, a gate dielectric being arranged between the gate electrode and the silicon substrate; forming a doped pocket region below the gate dielectric adjacent to the source region; forming a selectively silicidated region in the source region, the selectively silicidated region extending as far as to below a gate; and forming a counter-doped region doped in an opposite way to the pocket region adjacent to the pocket region in the source region by diffusion of dopants out of the silicidated region, as a result of which a tunnel junction parallel to the electric field lines of the gate electrode is achieved.

First claim

The invention claimed is:

1. A method for producing a tunnel field-effect transistor (TFET) comprising a source region, a channel region, and a drain region, the method comprising:
arranging an epitaxial layer on a silicon substrate;
applying a gate arrangement having a gate electrode to the epitaxial layer, a gate dielectric being arranged between the gate electrode and the silicon substrate;
forming a doped pocket region below the gate dielectric adjacent to the source region;
forming a selectively silicided region in the source region, the selectively silicided region extending as far as to below a gate; and
forming a counter-doped region doped in an opposite way to the doped pocket region adjacent to the doped pocket region in the source region by diffusion of dopants out of the selectively silicided region, as a result of which a tunnel junction parallel to electric field lines of the gate electrode is achieved.

2. The method according to claim 1 , wherein at least one of Si—Ge, Ge, Ge—Sn, or Si—Ge—Sn is used for the epitaxial layer.

3. The method according to claim 1 , wherein the counter-doped region is produced by selective silicidation of the source region, subsequent doping, and subsequent diffusion of the dopants.

4. The method according claim 1 , wherein the counter-doped region is produced by doping the source region, subsequent selective silicidation, and subsequent diffusion of the dopants.

5. The method according to claim 1 , wherein the dopants diffuse out of the selectively silicided region as far as into the doped pocket region.

6. The method according to claim 1 , wherein the counter-doped region is formed so as to be self-adjusting.

7. The method according to claim 1 , wherein a planar Si substrate is used and the counter-doped region is produced below the doped pocket region.

8. The method according to claim 1 , wherein an Si nanowire is used and the counter-doped region is produced in the center of a circumferential doped pocket region.

9. The according to claim 1 , wherein the drain region is doped identically to the doped pocket region.

10. A tunnel field-effect transistor (TFET) produced according to the method according to claim 1 .

11. A tunnel field-effect transistor (TFET), comprising:
a silicon substrate;
an epitaxial layer arranged on the silicon substrate;
a gate arrangement arranged on the epitaxial layer, the gate arrangement having a gate electrode and a gate dielectric arranged between the gate electrode and the silicon substrate;
a channel arranged below the gate dielectric;
a drain region adjacent to the channel;
a pocket region arranged below the gate dielectric and adjacent to the channel; and
a source region adjacent to the pocket region;
wherein the source region includes a silicided region arranged at least partially below the gate arrangement,
wherein the source region includes a counter-doped region doped in an opposite way to the pocket region and arranged adjacent to the pocket region at least partially below the pocket region and adjacent to the silicided region by which there is a vertical tunnel junction parallel to the electric field lines of the gate electrode, and
wherein the counter-doped region is formed by dopants that have diffused out of the silicided region.

12. The tunnel field-effect transistor (TFET) according to claim 11 , wherein the epitaxial layer comprises at least one of Si—Ge, Ge, Ge—Sn, or Si—Ge—Sn.

13. The tunnel field-effect transistor (TFET) according to claim 11 , wherein the counter-doped region has a layer thickness of between 3 nm and 5 nm.

14. The tunnel field-effect transistor (TFET) according to claim 11 , wherein the silicon substrate is planar and wherein the counter-doped region is arranged below the pocket region.

15. The tunnel field-effect transistor (TFET) according to claim 11 , wherein the silicon substrate is a nanowire, wherein the pocket region is an annular pocket region, wherein the gate arrangement is arranged in an annular manner, and wherein the counter-doped region is arranged in the center of the pocket region.

16. The tunnel field-effect transistor (TFET) according to claim 15 , wherein the source region, the channel region and the drain region are formed inside the nanowire.

17. The tunnel field-effect transistor (TFET) according to claim 11 , wherein the pocket region has a dopant concentration of between 10 18 cm −3 and 10 20 cm −3 .

18. A tunnel field-effect transistor (TFET), comprising:
a silicon substrate;
an epitaxial layer arranged on the silicon substrate;
a gate arrangement arranged on the epitaxial layer, the gate arrangement having a gate electrode and a gate dielectric arranged between the gate electrode and the silicon substrate;
a channel arranged below the gate dielectric;
a drain region adjacent to the channel;
a pocket region arranged below the gate dielectric and adjacent to the channel; and
a source region adjacent to the pocket region;
wherein the source region includes a silicided region arranged at least partially below the gate arrangement,
wherein the source region includes a counter-doped region doped in an opposite way to the pocket region and arranged adjacent to the pocket region at least partially below the pocket region and adjacent to the silicided region by which there is a vertical tunnel junction parallel to the electric field lines of the gate electrode,
wherein the counter-doped region is formed by dopants that have diffused out of the silicided region, and
wherein the silicon substrate is a nanowire, wherein the pocket region is an annular pocket region, wherein the gate arrangement is arranged in an annular manner, and wherein the counter-doped region is arranged in the center of the pocket region.

19. The TFET according to claim 18 , wherein the source region, the channel region and the drain region are formed inside the nanowire.

Assignees

• Forschungszentrum Juelich Gmbh

Inventors

• Zhao Qing-Tai
• Mantl Siegfried
• Blaeser Sebastian

Classifications

• H01L29/78

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic

• H01L29/66356

  Electricity · mapped topic

• H01L29/0847 Primary

  Electricity · mapped topic