Heterojunction tunnel field effect transistor fabrication using limited lithography steps

Patent metadata

Field	Value
Publication number	US-9614042-B2
Application number	US-201514640280-A
Country	US
Kind code	B2
Filing date	Mar 6, 2015
Priority date	Mar 6, 2015
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A structure and method for fabricating a vertical heterojunction tunnel field effect transistor (TFET) using limited lithography steps is disclosed. The fabrication of a second conductivity type source/drain region may utilize a single lithography step to form a first-type source/drain region, and a metal contact thereon, adjacent to a gate stack having a first conductivity type source/drain region on an opposite side.

First claim

What is claimed is:

1. A method of forming a heterojunction tunnel field effect transistor (TFET) comprising:
forming a gate stack on a substrate;
forming first-type source/drain regions in the substrate on either side of the gate stack;
forming an interlevel dielectric (ILD) layer on the gate stack and the first-type source/drain regions;
forming a first opening in the ILD layer to expose an upper surface of one of the first-type source/drain regions;
removing the exposed first-type source-drain region to form a recess;
forming a second-type source/drain region in the recess, the second-type source/drain region having an opposite conductivity type as the first-type source/drain regions;
forming a first contact liner on the second-type source/drain region, the gate stack, and a vertical sidewall of the ILD layer; and
forming a first contact on the first contact liner.

2. The method of claim 1 , further comprising:
forming a second opening in the ILD layer to expose an upper surface of the first-type source/drain region;
forming a second contact liner on the first-type source/drain region, the gate stack, and a vertical sidewall of the ILD layer;
forming a second contact on the second contact liner.

3. The method of claim 1 , further comprising:
forming undercut regions in the recess, extending below the gate stack, using an intrinsic layer controllable digital etch.

4. The method of claim 1 , wherein the first-type source/drain regions comprise n-doped silicon germanium (SiGe).

5. The method of claim 1 , wherein the second-type source/drain region comprises p-doped gallium antimonide (GaSb).

6. The method of claim 1 , further comprising:
forming an isolation region in the substrate adjacent to the first-type source/drain region.

7. A method of claim 1 , wherein the forming the gate stack on the substrate comprises:
forming a gate dielectric layer on the substrate;
forming a gate electrode on the gate dielectric layer;
forming a cap on the gate electrode; and
forming spacers on the substrate, the spacers contacting a sidewall of the gate dielectric layer, a sidewall of the gate electrode, and a sidewall of the cap.

8. The method of claim 2 , wherein the first opening and the second opening are formed in a single step.

Assignees

• IBM

Inventors

• Leobandung Effendi

Classifications

• H01L29/0847

  Electricity · mapped topic

• H01L29/267 Primary

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title