Method for manufacturing semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10438958-B2
Application number	US-201815871074-A
Country	US
Kind code	B2
Filing date	Jan 15, 2018
Priority date	May 26, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A method for manufacturing a semiconductor memory device including following steps is provided. A substrate having a first region, a second region, and a third region is provided. A first stack structure is formed on the first region. A second stack structure is formed on the second region. A third stack structure is formed on the third region. A first mask layer is formed on the substrate to cover the third stack structure. A first ion implantation process is performed, so that a second floating gate and a second control gate in the second stack structure are changed to a first conductive type. A second mask layer formed on the substrate to cover the first and second stack structures. A second ion implantation process is performed, so that a third floating gate and a third control gate in the third stack structure are changed as a second conductive type.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor memory device, comprising:
providing a substrate, wherein the substrate has a first region, a second region and a third region;
forming a first stack structure on the first region, wherein the first stack structure sequentially comprises a first gate dielectric layer, a first floating gate, a first inter-gate dielectric layer and a first control gate;
forming a second stack structure on the second region, wherein the second stack structure sequentially comprises a second gate dielectric layer, a second floating gate, a second inter-gate dielectric layer and a second control gate;
forming a third stack structure on the third region, wherein the third stack structure sequentially comprises a third gate dielectric layer, a third floating gate, a third inter-gate dielectric layer and a third control gate;
forming a dielectric layer on the substrate, wherein the dielectric layer covers a top surface of the substrate and exposes top surfaces of the first control gate, the second control gate, and the third control gate;
forming a first mask layer on the dielectric layer and the top surface of the third control gate;
performing a first ion implantation process by using the dielectric layer and the first mask layer as a mask, so that conductive types of the first control gate, the second floating gate, and the second control gate are changed to a first conductive type via the same ion implantation process;
removing the first mask layer, and forming a second mask layer on the dielectric layer and the top surfaces of the first control gate and the second control gate; and
performing a second ion implantation process by using the dielectric layer and the second mask layer as a mask, so that conductive types of the third floating gate and the third control gate are changed to a second conductive type.

2. The method for manufacturing the semiconductor memory device as claimed in claim 1 , wherein before the first ion implantation process and the second ion implantation process are performed, the method further comprises:
forming a first source/drain in the substrate at two sides of the first stack structure, forming a second source/drain in the substrate at two sides of the second stack structure and forming a third source/drain in the substrate at two sides of the third stack structure.

3. The method for manufacturing the semiconductor memory device as claimed in claim 1 , wherein after the second ion implantation process is performed, the method further comprises:
removing the second mask layer;
forming a metal layer on the substrate to cover surfaces of the first control gate, the second control gate and the third control gate; and
performing a metal silicification process to form a first metal silicide layer on the first control gate, to form a second metal silicide layer on the second control gate and to form a third metal silicide layer on the third control gate.

4. The method for manufacturing the semiconductor memory device as claimed in claim 1 , wherein thicknesses of the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer are different to each other.

5. The method for manufacturing the semiconductor memory device as claimed in claim 1 , wherein the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer, and the thickness of the first gate dielectric layer is greater than the thickness of the third gate dielectric layer.

6. The method for manufacturing the semiconductor memory device as claimed in claim 5 , wherein the first region is a cell region, the second region is a high-voltage device region, and the third region is a low-voltage device region.

7. The method for manufacturing the semiconductor memory device as claimed in claim 1 , wherein the first control gate and the second control gate have the same doping concentration.

8. The method for manufacturing the semiconductor memory device as claimed in claim 1 , wherein the first conductive type is different from the second conductive type.

9. The method for manufacturing the semiconductor memory device as claimed in claim 1 , wherein the first stack structure, the second stack structure and the third stack structure are separated from each other and not connected to each other.

10. The method for manufacturing the semiconductor memory device as claimed in claim 1 , wherein the semiconductor memory device is a flash memory.

Assignees

• Winbond Electronics Corp

Inventors

• Yang Cheng-Ta
• Chiang Lu-Ping

Classifications

• H01L27/11541

  Electricity · mapped topic

• H01L27/11546

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11543

  Electricity · mapped topic

• H01L27/11539

  Electricity · mapped topic