Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10283512-B2
Application number	US-201715584314-A
Country	US
Kind code	B2
Filing date	May 2, 2017
Priority date	Nov 29, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device including a non-volatile memory, the method comprising:
forming a cell structure, the cell structure including:
a stacked structure including a first poly silicon layer disposed over a first dielectric layer, a second dielectric layer disposed over the first polysilicon layer, a third dielectric layer disposed over the second dielectric layer, and a second polysilicon layer disposed over the third dielectric layer; and
third poly silicon layers disposed at both sides of the stacked structure;

at least partially removing the second polysilicon layer, thereby forming a control gate space; and
forming a conductive material in the control gate space,
wherein the forming the cell structure comprises:
forming the first dielectric layer over a substrate;
forming a first polysilicon film for the first polysilicon layer over the first dielectric layer;
forming a second dielectric film for the second dielectric layer over the first polysilicon film;
forming a third dielectric film for the third dielectric layer over the second dielectric film;
forming a second polysilicon film for the second polysilicon layer over the third dielectric film;
patterning the second polysilicon film and the third dielectric film, thereby forming the second polysilicon layer and the third dielectric layer;
after the second polysilicon layer and the third dielectric layer are formed, patterning the second dielectric film and the first polysilicon film, thereby forming the stacked structure;
forming a third polysilicon layer for the third polysilicon layers at both sides of the stacked structure; and
performing a planarization operation on the stacked structure and the third polysilicon layer.

2. The method of claim 1 , wherein the third dielectric layer includes one or more oxide layers of Hf, Y, Ta, Ti, Al and Zr.

3. The method of claim 2 , wherein the third dielectric layer further includes a silicon oxide layer.

4. The method of claim 1 , wherein the second dielectric layer is a silicon oxide layer, a silicon nitride layer or multilayers thereof.

5. The method of claim 1 , wherein the first dielectric layer is silicon oxide.

6. The method of claim 1 , further comprising, after the second polysilicon film and the third dielectric film are patterned and before the second dielectric film and the first polysilicon film are patterned, forming first sidewall spacers on both sides of the patterned second polysilicon film.

7. The method of claim 6 , further comprising, after the first sidewall spacers are formed and before the second dielectric film and the first polysilicon film are patterned, forming second sidewall spacers over the first sidewall spacers.

8. The method of claim 7 , wherein the third sidewall spacers include one of a silicon oxide layer, a silicon nitride layer and multilayers thereof.

9. The method of claim 1 , wherein:
when the second polysilicon layer is at least partially removed, the third polysilicon layers are also at least partially removed, thereby forming select gate spaces and an erase gate space, and
the conductive material is also formed in the select gate spaces and the erase gate space, thereby forming a select gate and an erase gate.

10. A method for manufacturing a semiconductor device including a non-volatile memory disposed in a memory cell area and a field effect transistor disposed in a logic circuit area, the method comprising:
forming a cell structure for the non-volatile memory in the memory cell area, the cell structure comprising:
a stacked structure including a first poly silicon layer disposed over a first dielectric layer, a second dielectric layer disposed over the first polysilicon layer, a third dielectric layer disposed over the second dielectric layer, and a second polysilicon layer disposed over the third dielectric layer; and
third poly silicon layers disposed at both sides of the stacked structure;

forming a dummy gate structure for the field effect transistor in the logic circuit area, the dummy gate structure comprising:
a gate dielectric layer disposed over the substrate; and
a dummy logic gate made of polysilicon and disposed over the gate dielectric layer;

at least partially removing the second polysilicon layer in the memory cell area, thereby forming a control gate space and at least partially removing the dummy logic gate of the dummy logic gate, thereby forming a first logic gate space; and
forming a conductive material in the control gate space and the first logic gate space, wherein the cell structure and the dummy logic gate structure are formed by:
forming the first dielectric layer in the memory cell area;
forming a first polysilicon film for the first polysilicon layer over the first gate dielectric layer in the memory cell area;
forming a second dielectric film for the second dielectric layer over the first polysilicon film in the memory cell area;
after the second dielectric film is formed, forming a third dielectric film for the third dielectric layer and the gate dielectric layer in the memory cell area and the logic circuit area;
forming a second polysilicon film for the second polysilicon layer and the dummy logic gate over the second dielectric film in the memory cell area and the logic circuit area;
patterning the second polysilicon film and the third dielectric film in the memory cell area, thereby forming the second polysilicon layer and patterning the second polysilicon film and the third dielectric film in the logic circuit area, thereby forming the dummy logic gate and the gate dielectric layer;
after the second polysilicon layer and the third dielectric layer are patterned, patterning the second dielectric film and the first polysilicon film in the memory cell area, thereby forming the stacked structure in the memory cell area;
forming a third polysilicon film for the third polysilicon layers; and
performing a planarization operation on the stacked structure, the third polysilicon layer and the dummy logic gate, and
the third dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

11. The method of claim 10 , wherein the third dielectric layer includes one or more oxide layers of Hf, Y, Ta, Ti, Al and Zr.

12. The method of claim 10 , wherein:
the second dielectric layer is one of a silicon oxide layer, a silicon nitride layer and multilayers thereof, and
the dummy logic gate does not include the second dielectric film.

13. The method of claim 10 , further comprising, after the second polysilicon film and the third dielectric film are patterned and before the second dielectric film and the first polysilicon film are patterned, forming first sidewall spacers on both sides of the second polysilicon layer and on both sides of the dummy logic gate.

14. The method of claim 13 , further comprising, after the first sidewall spacers are formed and before the second dielectric film and the first polysilicon film are patterned, forming second sidewall spacers over the first sidewall spacers.

15. The method of claim 14 , wherein the third sidewall spacers includes one of a silicon oxide layer, a silicon nitride layer and multilayers thereof.

16. The method of claim 10 , wherein:
when the second polysilicon layer is at least partially removed, the third polysilicon layers in the memory cell area are also at least partially removed, thereby forming a select gate space and an erase gate space, and
the conductive material is also formed in the select gate space and the erase gate space.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Wei Cheng
• Teng Li-Feng

Classifications

• H01L27/11539

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic

• H01L27/11526

  Electricity · mapped topic

• H01L27/11536

  Electricity · mapped topic