Integration of floating gate memory and logic device in replacement gate flow

Patent metadata

Field	Value
Publication number	US-10600795-B2
Application number	US-201815882502-A
Country	US
Kind code	B2
Filing date	Jan 29, 2018
Priority date	Aug 19, 2016
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

After forming a first sacrificial gate stack over a portion of a first semiconductor fin located in a logic device region of a substrate, and a second sacrificial gate stack over a portion of a second semiconductor fin located in a memory device region of the substrate, in which each of the first sacrificial gate stack and the second sacrificial gate stack includes, from bottom to top, a tunneling oxide portion, a floating gate electrode, a control oxide portion, a gate conductor and a gate cap, an entirety of the first sacrificial gate stack is removed to provide a first gate cavity, and only the gate cap and the gate conductor are removed from the second sacrificial gate stack to provide a second gate cavity. Next, a high-k gate dielectric and a gate electrode are formed within each of the first gate cavity and the second gate cavity.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a logic transistor located in a logic device region of a substrate, the logic transistor comprising:
a first functional gate stack contacting a first body region of a first semiconductor fin and including a first high-k gate dielectric and a first gate electrode surrounded by the first high-k gate dielectric, and
first source/drain regions located within the first semiconductor fin and laterally surrounding the first body region;

a non-volatile memory transistor located in a memory device region of the substrate, the non-volatile memory transistor comprising:
a second functional gate stack contacting a second body region of a second semiconductor fin and including a tunnel oxide portion, a floating gate electrode, a control oxide portion, a second high-k gate dielectric and a second gate electrode surrounded by the second high-k gate dielectric, and
second source/drain regions located within the second semiconductor fin and laterally surrounding the second body region;

an interlevel dielectric (ILD) layer laterally surrounding the first functional gate stack and the second functional gate stack;
a first source/drain contact structure contacting a topmost surface of each of the first source/drain regions and embedded in the ILD layer; and
a second source/drain contact structure contacting a topmost surface of each of the second source/drain regions and embedded in the ILD layer, wherein each of the first source/drain contact structure and the second source/drain contact structure has a topmost surface that is coplanar with a topmost surface of the ILD layer and coplanar with a topmost surface of each of the first high-k gate dielectric, the first gate electrode, the second high-k gate dielectric and the second gate electrode.

2. The semiconductor structure of claim 1 , wherein each of the first high-k gate dielectric and the second high-k gate dielectric is a U-shaped gate dielectric.

3. The semiconductor structure of claim 1 , wherein the first functional gate stack further comprises a first work function material portion located between the first high-k gate dielectric and the first gate electrode, and the second functional gate stack further comprises a second work function material portion located between the second high-k gate dielectric and the second gate electrode.

4. The semiconductor structure of claim 1 , wherein each of the tunneling oxide portion and the control oxide portion comprises silicon dioxide, and the floating gate electrode comprises polysilicon.

5. The semiconductor structure of claim 1 , further comprising a shallow trench isolation layer located on the substrate and between the first semiconductor fin and the second semiconductor fin, wherein the shallow trench isolation layer has a height that is less than a height of the first and second semiconductor fins.

6. The semiconductor structure of claim 1 , wherein the substrate comprises a semiconductor material.

7. The semiconductor structure of claim 1 , wherein the substrate has an upper portion that is composed of an insulator layer, and wherein the first and second semiconductor fins are located directly on the insulator layer.

8. The semiconductor structure of claim 1 , wherein the topmost surface of each of first high-k gate dielectric, the first gate electrode, the second high-k gate dielectric and the second gate electrode are coplanar with each other.

9. The semiconductor structure of claim 1 , wherein a bottommost surface of the first high-k gate dielectric is in direct contact with the first body region of the first semiconductor fin, and wherein a bottommost surface of the second high-k gate dielectric is direct contact with the control oxide portion.

10. The semiconductor structure of claim 1 , further comprising a first gate spacer located on sidewalls of the first functional gate stack and having a bottommost surface located on a topmost surface of the first source/drain regions, and a second gate spacer located on sidewalls of the second functional gate stack and having a bottommost surface located on a topmost surface of the second source/drain regions.

11. The semiconductor structure of claim 1 , wherein the tunnel oxide portion, the floating gate electrode and the control oxide portion have outermost surfaces that are vertically aligned to outermost sidewalls of the second high-k gate dielectric.

12. The semiconductor structure of claim 1 , wherein the logic transistor further comprises a first gate spacer located on sidewalls of the first functional gate stack, wherein vertical portions of the first high-k gate dielectric are in contact with the first gate spacer.

13. The semiconductor structure of claim 1 , wherein the non-volatile memory transistor further comprises a second gate spacer located on sidewalls of the second functional gate stack, wherein sidewalls of the tunneling oxide portion, the floating gate electrode and the control oxide portion are in contact with lower portions of the second gate spacer, and vertical portions of the second high-k gate dielectric are in contact with upper portions of the second gate spacer.

14. A semiconductor structure comprising:
a logic transistor located in a logic device region of a substrate, the logic transistor comprising:
a first functional gate stack contacting a first body region of a first semiconductor fin and including a U-shaped first high-k gate dielectric and a first gate electrode surrounded by the U-shaped first high-k gate dielectric, and
first source/drain regions located within the first semiconductor fin and laterally surrounding the first body region;

a non-volatile memory transistor located in a memory device region of the substrate, the non-volatile memory transistor comprising:
a second functional gate stack contacting a second body region of a second semiconductor fin and including a tunnel oxide portion, a floating gate electrode, a control oxide portion, a second U-shaped high-k gate dielectric and a second gate electrode surrounded by the second U-shaped high-k gate dielectric, wherein the tunnel oxide portion, the floating gate electrode and the control oxide portion have outermost surfaces that are vertically aligned to outermost sidewalls of the second U-shaped high-k gate dielectric, and
second source/drain regions located within the second semiconductor fin and laterally surrounding the second body region;

an interlevel dielectric (ILD) layer laterally surrounding the first functional gate stack and the second functional gate stack;
a first source/drain contact structure contacting a topmost surface of each of the first source/drain regions and embedded in the ILD layer; and
a second source/drain contact structure contacting a topmost surface of each of the second source/drain regions and embedded in the ILD layer, wherein each of the first source/drain contact structure and the second source/drain contact structure has a topmost surface that is coplanar with a topmost surface of the ILD layer and coplanar with a topmost surface of each of the first U-shaped high-k gate dielectric, the first gate electrode, the second U-shaped high-k gate dielectric and the second Rate electrode.

15. The semiconductor structure of claim 14 , wherein the logic transistor further comprises a first gate spacer located on sidewalls of the first functional gate stack, wherein vertical portions of the first U-shaped high-k gate dielectric are in contact with the first gate spacer.

16. The semiconductor structure of claim 14 , wherein the non-volatile memory transistor further compr

Assignees

• IBM

Inventors

• Leobandung Effendi

Classifications

• H01L29/66545

  Electricity · mapped topic

• H01L29/7881

  Electricity · mapped topic

• H01L29/513

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L27/11536

  Electricity · mapped topic