Transistor

Patent metadata

Field	Value
Publication number	US-12575136-B2
Application number	US-202318158176-A
Country	US
Kind code	B2
Filing date	Jan 23, 2023
Priority date	Jan 27, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A transistor includes an oxide semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the oxide semiconductor layer, a gate electrode spaced apart from the oxide semiconductor layer, a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode, and a graphene layer disposed between the gate electrode and the gate insulating layer and doped with a metal.

First claim

What is claimed is:

1 . A transistor comprising:
an oxide semiconductor layer; a source electrode and a drain electrode spaced apart from each other on the oxide semiconductor layer; a gate electrode spaced apart from the oxide semiconductor layer; a gate insulating layer between the oxide semiconductor layer and the gate electrode; and a graphene layer between the gate electrode and the gate insulating layer and doped with a metal.

2 . The transistor of claim 1 , wherein the metal doped in the graphene layer is different from a metal included in the oxide semiconductor layer.

3 . The transistor of claim 1 , wherein the metal doped into the graphene layer includes at least one of ruthenium (Ru), aluminum (Al), titanium (Ti), platinum (Pt), thallium (Tl), tantalum (Ta), rhodium (Rh), iridium (Ir), cobalt (Co), and tungsten (W).

4 . The transistor of claim 1 , wherein the metal is doped into the graphene layer in an amount of 0.2 at % or more and 5 at % or less with respect to a total amount of the graphene layer.

5 . The transistor of claim 1 , wherein a work function of the graphene layer is greater or equal to 4.9 eV or and less than or equal to 5.1 eV.

6 . The transistor of claim 1 , wherein a threshold voltage of the transistor is positive when a current flowing from the drain electrode to the source electrode is about 10 −12 A/micron.

7 . The transistor of claim 1 , wherein a thickness of the graphene layer is less than a thickness of the gate electrode.

8 . The transistor of claim 1 , wherein a thickness of the graphene layer is less than or equal to 10 nm.

9 . The transistor of claim 1 , wherein the graphene layer is in contact with two or more surfaces of the gate electrode.

10 . The transistor of claim 1 , wherein the graphene layer is in contact with a lower surface of the gate electrode and a side surface of the gate electrode.

11 . The transistor of claim 1 , wherein the gate insulating layer at least partially covers two or more surfaces of the gate electrode.

12 . The transistor of claim 1 , wherein the gate insulating layer at least partially covers a lower surface of the gate electrode and a side surface of the gate electrode.

13 . The transistor of claim 1 , wherein the gate insulating layer is in contact with at least one of the source electrode and the drain electrode.

14 . The transistor of claim 1 , wherein at least one of the source electrode and the drain electrode includes a stepped shape.

15 . The transistor of claim 1 , wherein at least one of the source electrode and the drain electrode includes a first region having a first thickness and a second region having a second thickness less than the first thickness, and the second region is closer to the gate electrode than the first region.

16 . The transistor of claim 1 , wherein the source electrode, the drain electrode, and the gate insulating layer are in contact with a same surface of the oxide semiconductor layer.

17 . The transistor of claim 1 , wherein the source electrode and the drain electrode are on a first surface of the oxide semiconductor layer, and the gate insulating layer is on a second surface, different from the first surface of the oxide semiconductor layer.

18 . The transistor of claim 1 , wherein
the gate insulating layer includes a first gate insulating layer in contact with a first surface of the oxide semiconductor layer and a second gate insulating layer in contact with a second surface different from the first surface of the oxide semiconductor layer, the gate electrode includes a first gate electrode on the first gate insulating layer and a second gate electrode on the second gate insulating layer, and the graphene layer includes a first graphene layer between the first gate insulating layer and the first gate electrode and a second graphene layer between the second gate insulating layer and the second gate electrode.

19 . The transistor of claim 1 , wherein the source electrode, the oxide semiconductor layer, and the drain electrode are sequentially arranged in one direction.

20 . The transistor of claim 1 , wherein the gate insulating layer entirely surrounds a side surface of the oxide semiconductor layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Sangwook
• Byun Kyung-Eun
• Shin Keunwook
• Jung Moonil
• Kim Euntae
• Yang Jeeeun
• Lee Kwanghee

Classifications

• H10D62/882

  Graphene · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10D30/6704

  having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device · CPC title