Graphene devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9306021-B2
Application number	US-201414244223-A
Country	US
Kind code	B2
Filing date	Apr 3, 2014
Priority date	Apr 5, 2013
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

A graphene device includes: a semiconductor substrate having a first region and a second region; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on the second region of the semiconductor substrate. The semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate.

First claim

What is claimed is:

1. A graphene device comprising:
a semiconductor substrate having a first region and a second region;
a graphene layer on the first region, but not on the second region of the semiconductor substrate;
a first electrode on a first portion of the graphene layer;
a second electrode on a second portion of the graphene layer;
an insulating layer between the graphene layer and the second electrode; and
a third electrode directly on the semiconductor substrate, and entirely within the second region of the semiconductor substrate; wherein
the semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate,
the first portion of the graphene layer is on the first region of the semiconductor substrate, and
the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties.

2. The graphene device of claim 1 , wherein the graphene layer directly contacts the semiconductor substrate.

3. The graphene device of claim 1 , wherein the first electrode directly contacts the graphene layer.

4. The graphene device of claim 1 , wherein a surface of the first region of the semiconductor substrate is flat.

5. The graphene device of claim 1 , wherein the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode.

6. The graphene device of claim 1 , wherein the semiconductor substrate has a carrier concentration of between about 10 15 and about 10 17 cm −1 , inclusive.

7. The graphene device of claim 1 , further comprising:
a high-concentration doped region in the semiconductor substrate, the high-concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate.

8. The graphene device of claim 7 , wherein the high-concentration doped region is positioned in a lower part of the second region of the semiconductor substrate and in a third region of the semiconductor substrate, the third region being between the first and second regions of the semiconductor substrate.

9. The graphene device of claim 8 , wherein the third electrode electrically contacts the high-concentration doped region through a hole in the third region of the semiconductor substrate.

10. The graphene device of claim 7 , wherein the high-concentration doped region has a carrier concentration of between about 10 18 and about 10 20 cm −1 , inclusive.

11. The graphene device of claim 7 , wherein a conductivity type of impurities doped into the semiconductor substrate and a conductivity type of the impurities doped into the high-concentration doped region are the same.

12. The graphene device of claim 7 , wherein an upper surface of the high-concentration doped region is exposed and electrically contacts the third electrode.

13. The graphene device of claim 1 , wherein the first electrode includes at least one of gold, nickel, platinum, aluminum, and chromium.

14. The graphene device of claim 1 , wherein the second and third electrodes include metal or polysilicon.

15. The graphene device of claim 1 , wherein the semiconductor substrate is formed of one of silicon, germanium, silicon-germanium, III-V-group semiconductor, and II-VI-group semiconductor.

16. The graphene device of claim 1 , wherein the tunable Schottky barrier varies according to a voltage applied to the second electrode.

17. The graphene device of claim 1 , wherein the tunable Schottky barrier decreases in response to a voltage applied to the second electrode.

18. A graphene device comprising:
a semiconductor substrate;
a graphene layer directly on a first region of the semiconductor substrate;
a first electrode on a first portion of the graphene layer, a junction between the graphene layer and the semiconductor substrate forming a Schottky barrier of the semiconductor substrate;
a second electrode on a second portion of the graphene layer;
an insulating layer between the graphene layer and the second electrode; and
a third electrode on a second region of the semiconductor substrate, wherein
an entirety of the third electrode is directly on the semiconductor substrate,
the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties, and
the first portion of the graphene layer is on the first region of the semiconductor substrate.

19. The graphene device of claim 18 , wherein the first electrode directly contacts the graphene layer.

20. The graphene device of claim 18 , wherein a surface of the first region of the semiconductor substrate is flat.

21. The graphene device of claim 18 , wherein the Schottky barrier is a tunable Schottky barrier.

22. The graphene device of claim 18 , wherein the Schottky barrier varies according to a voltage applied to the second electrode.

23. The graphene device of claim 18 , further comprising:
a high-concentration doped region in the semiconductor substrate, the high-concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate.

24. A graphene device comprising:
a semiconductor substrate;
a graphene layer on a flat surface of a first region of the semiconductor substrate;
a first electrode on a first portion of the graphene layer, a junction between the graphene layer and the semiconductor substrate forming a Schottky barrier of the semiconductor substrate;
a second electrode on a second portion of the graphene layer;
an insulating layer between the graphene layer and the second electrode; and
a third electrode on a second region of the semiconductor substrate, wherein
an entirety of the third electrode is on the semiconductor substrate without an intervening layer,
the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties, and
the first portion of the graphene layer is on the first region of the semiconductor substrate.

25. The graphene device of claim 24 , the Schottky barrier varies according to a voltage applied to the second electrode.

26. The graphene device of claim 24 , wherein the Schottky barrier is a tunable Schottky barrier.

27. The graphene device of claim 24 , further comprising:
a high-concentration doped region in the semiconductor substrate, the high-concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Hyun-Jong
• Seo David
• Park Seong-Jun
• Byun Kyung-Eun
• Song Hyun-Jae
• Yang Hee-Jun
• Heo Jin-Seong

Classifications

• H10W15/01

  Manufacture or treatment · CPC title

• H10W15/00

  Highly-doped buried regions of integrated devices · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• C01B32/182

  Graphene · CPC title

• H10D62/882 Primary

  Graphene · CPC title