Imaging device and electronic device

Patent metadata

Field	Value
Publication number	US-10192913-B2
Application number	US-201715639567-A
Country	US
Kind code	B2
Filing date	Jun 30, 2017
Priority date	Oct 24, 2014
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

An imaging device with excellent imaging performance is provided. In the imaging device, a first layer, a second layer, and a third layer have a region overlapping with one another, the first layer and the second layer each include transistors, and the third layer includes a photoelectric conversion element. Off-state currents of the transistors formed in the first layer are lower than those of the transistors formed in the second layer, and field-effect mobilities of the transistors formed in the second layer are higher than those of the transistors formed in the first layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first layer;
a second layer; and
a third layer,
wherein the first layer, the second layer, and the third layer overlap with one another,
wherein the first layer comprises a first transistor and a second transistor,
wherein the second layer comprises a third transistor and a fourth transistor,
wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises an oxide semiconductor in a channel formation region,
wherein the third layer comprises a photoelectric conversion element,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the second transistor is electrically connected to a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein one electrode of the photoelectric conversion element is electrically connected to the other one of the source and the drain of the first transistor,
wherein each of off-state current of the first transistor and off-state current of the second transistor are lower than each of off-state current of the third transistor and off-state current of the fourth transistor, and
wherein each of on-state current of the third transistor and on-state current of the fourth transistor are higher than on-state current of the first transistor and on-state current of the second transistor.

2. The semiconductor device according to claim 1 ,
wherein the second layer is over the first layer, and
wherein the third layer is over the second layer.

3. The semiconductor device according to claim 1 ,
wherein the first layer is over the second layer, and
wherein the third layer is over the first layer.

4. The semiconductor device according to claim 1 ,
wherein each of the oxide semiconductor of the third transistor and the oxide semiconductor of the fourth transistor have smaller bandgap than each of the oxide semiconductor of the first transistor and the oxide semiconductor of the second transistor.

5. The semiconductor device according to claim 1 ,
wherein each of the oxide semiconductor of the third transistor and the oxide semiconductor of the fourth transistor are thicker than each of the oxide semiconductor of the first transistor and the oxide semiconductor of the second transistor.

6. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor includes In, Zn, and M, and
wherein M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

7. The semiconductor device according to claim 1 ,
wherein the photoelectric conversion element includes a photoelectric conversion layer including selenium or a compound containing selenium.

8. A semiconductor device comprising:
a first layer;
a second layer; and
a third layer,
wherein the first layer, the second layer, and the third layer overlap with one another,
wherein the first layer comprises a first transistor and a second transistor,
wherein the second layer comprises a third transistor and a fourth transistor,
wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises an oxide semiconductor in a channel formation region,
wherein the third layer comprises a photoelectric conversion element,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the second transistor is electrically connected to a gate of the third transistor,
wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein one electrode of the photoelectric conversion element is electrically connected to the other one of the source and the drain of the first transistor, and
wherein each of the bandgap of the channel formation region of the third transistor and the bandgap of the channel formation region of the fourth transistor are smaller than each of the bandgap of the channel formation region of the first transistor and the bandgap of the channel formation region of the second transistor.

9. The semiconductor device according to claim 8 ,
wherein the second layer is over the first layer, and
wherein the third layer is over the second layer.

10. The semiconductor device according to claim 8 ,
wherein the first layer is over the second layer, and
wherein the third layer is over the first layer.

11. The semiconductor device according to claim 8 ,
wherein each of the oxide semiconductor of the third transistor and the oxide semiconductor of the fourth transistor are thicker than each of the oxide semiconductor of the first transistor and the oxide semiconductor of the second transistor.

12. The semiconductor device according to claim 8 ,
wherein the oxide semiconductor includes In, Zn, and M, and
wherein M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

13. The semiconductor device according to claim 8 ,
wherein the photoelectric conversion element includes a photoelectric conversion layer including selenium or a compound containing selenium.

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• H01L27/1225

  Electricity · mapped topic

• H01L31/0272

  Electricity · mapped topic

• H01L27/14667

  Electricity · mapped topic

• H01L27/14632

  Electricity · mapped topic

• H01L27/1255

  Electricity · mapped topic