Memory device and electronic device

Patent metadata

Field	Value
Publication number	US-10522693-B2
Application number	US-201614988804-A
Country	US
Kind code	B2
Filing date	Jan 6, 2016
Priority date	Jan 16, 2015
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A memory device with excellent writing performance and excellent storing performance is provided. In the memory device, a first layer overlaps with a second layer. The first layer includes a first transistor including an oxide semiconductor as an active layer. The second layer includes a second transistor and a third transistor each including an oxide semiconductor as an active layer. The off-state current of a transistor formed in the first layer is lower than the off-state current of each of a transistor formed in the second layer. The field-effect mobility of the transistor formed in the second layer is higher than the field-effect mobility of the transistor formed in the first layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory device comprising:
a first layer;
a second layer; and
a signal line,

wherein the first layer vertically overlaps with the second layer,
wherein the first layer comprises a first transistor comprising an oxide semiconductor as an active layer,
wherein the second layer comprises a second transistor and a third transistor each comprising an oxide semiconductor as an active layer,
wherein one of a source and a drain of the first transistor is directly connected to a gate of the second transistor,
wherein one of a source and a drain of the second transistor is directly connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the first transistor is directly connected to the signal line,
wherein the off-state current of the first transistor is lower than the off-state current of each of the second and third transistors,
wherein the field-effect mobility of each of the second and third transistors is higher than the field-effect mobility of the first transistor,
wherein a thickness of a gate insulating film of the first transistor is greater than a thickness of a gate insulating film of each of the second and third transistors, and
wherein the memory device is configured to store data in a node where the one of the source and the drain of the first transistor and the gate of the second transistor are directly connected.

2. The semiconductor device according to claim 1 , wherein the active layer of the first transistor has a wider band gap than the active layer of each of the second and third transistors.

3. The semiconductor device according to claim 1 , wherein the active layer of the second transistor and the active layer of the third transistor each have a greater thickness than the active layer of the first transistor.

4. The semiconductor device according to claim 1 , wherein a node where the one of the source and the drain of the first transistor and the gate of the second transistor are directly connected is configured to store a signal.

5. The semiconductor device according to claim 1 , wherein the one of the source and the drain of the first transistor is directly connected to one electrode of a capacitor.

6. The semiconductor device according to claim 1 ,
wherein the oxide semiconductor contains In, Zn, and M where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

7. An electronic device comprising:
the semiconductor device according to claim 1 and a display device.

8. A semiconductor device comprising:
a memory device comprising:
a first layer;
a second layer;
a third layer; and
a signal line,

wherein the first layer comprises a first transistor comprising an oxide semiconductor as an active layer,
wherein the second layer comprises a second transistor and a third transistor each comprising an oxide semiconductor as an active layer,
wherein the third layer comprises a fourth transistor comprising silicon as an active region or an active layer,
wherein one of a source and a drain of the first transistor is directly connected to a gate of the second transistor,
wherein one of a source and a drain of the second transistor is directly connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the first transistor is directly connected to the signal line,
wherein the off-state current of the first transistor is lower than the off-state current of each of the second and third transistors,
wherein the field-effect mobility of each of the second and third transistors is higher than the field-effect mobility of the first transistor,
wherein the first to third transistors are components of a first circuit,
wherein the fourth transistor is a component of a second circuit,
wherein a thickness of a gate insulating film of the first transistor is greater than a thickness of a gate insulating film of each of the second and third transistors, and
wherein the memory device is configured to store data in a node where the one of the source and the drain of the first transistor and the gate of the second transistor are directly connected.

9. The semiconductor device according to claim 8 , wherein the active layer of the first transistor has a wider band gap than the active layer of each of the second and third transistors.

10. The semiconductor device according to claim 8 , wherein the active layer of the second transistor and the active layer of the third transistor each have a greater thickness than the active layer of the first transistor.

11. The semiconductor device according to claim 8 , wherein the first layer, the second layer, and the third layer are stacked in the order of the first layer, the second layer, and the third layer or in the order of the second layer, the first layer, and the third layer.

12. The semiconductor device according to claim 8 , wherein the first circuit is configured to store a signal and the second circuit is configured to drive the first circuit.

13. The semiconductor device according to claim 8 , wherein the one of the source and the drain of the first transistor is directly connected to one electrode of a capacitor.

14. The semiconductor device according to claim 8 ,
wherein the oxide semiconductor contains In, Zn, and M where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

15. An electronic device comprising:
the semiconductor device according to claim 8 and a display device.

16. A semiconductor device comprising:
a memory device comprising:
a first layer;
a second layer;
a third layer; and
a signal line,

wherein the first layer comprises a first transistor comprising an oxide semiconductor as an active layer,
wherein the second layer comprises a second transistor, a third transistor, and a fourth transistor each comprising an oxide semiconductor as an active layer,
wherein the third layer comprises a fifth transistor comprising silicon as an active region or an active layer,
wherein one of a source and a drain of the first transistor is directly connected to a gate of the second transistor,
wherein one of a source and a drain of the second transistor is directly connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the first transistor is directly connected to the signal line,
wherein the off-state current of the first transistor is lower than the off-state current of each of the second, third, and fourth transistors,
wherein the field-effect mobility of each of the second and third transistors is higher than the field-effect mobility of the first transistor,
wherein the first to third transistors are components of a first circuit, and
wherein the fourth transistor and the fifth transistor are components of a second circuit,
wherein a thickness of a gate insulating film of the first transistor is greater than a thickness of a gate insulating film of each of the second and third transistors, and
wherein the memory device is configured to store data in a node where the one of the source and the drain of the first transistor and the gate of the second transistor are directly connected.

17. The semiconductor device according to claim 16 , wherein the active layer of the first transistor has a wider band gap than the active layer of each of the second, third, and fourth transistors.

18. The semiconductor device according to claim 16 , wherein the active layer of each of the second, third, and fourth transistors has a gre

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• H01L27/1255

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic

• H01L27/1207

  Electricity · mapped topic

• H01L27/1225

  Electricity · mapped topic

• H01L27/1237

  Electricity · mapped topic