Nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-12568619-B2
Application number	US-202218085717-A
Country	US
Kind code	B2
Filing date	Dec 21, 2022
Priority date	Dec 4, 2019
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A nonvolatile memory device includes; a memory cell area including a common source plate, at least one cell structure under the common source plate, and a first metal pad under the at least one cell structure, and a peripheral circuit area on which the memory cell area is mounted, including a middle area , a first edge area, and a second metal pad on the first edge area. The memory cell area further includes a first contact extending from the common source plate and connected to the first metal pad. The peripheral circuit area further includes a second contact extending from a common source line switch and connected to the second metal pad. The first metal pad contacts with the second metal pad on the second metal pad.

First claim

What is claimed is:

1 . A nonvolatile memory device comprising:
a memory cell area including a common source plate, at least one cell structure under the common source plate, and a first metal pad under the at least one cell structure; and a peripheral circuit area on which the memory cell area is mounted, including a middle area, a first edge area, and a second metal pad on the first edge area, the second metal pad contacting the first metal pad, wherein the memory cell area further includes a first contact extending from the common source plate and connected to the first metal pad, wherein the peripheral circuit area further includes a second contact extending from a common source line switch and connected to the second metal pad, and wherein the second contact is directly connected between the common source line switch and the second metal pad without a horizontal extension.

2 . The nonvolatile memory device of claim 1 , wherein the middle area is centrally disposed on the peripheral circuit area, and
the peripheral circuit area further includes a second edge area, wherein the first edge area and the second edge area are disposed on opposing sides of the middle area.

3 . The nonvolatile memory device of claim 1 , wherein the memory cell area further includes a third metal pad under the at least one cell structure,
wherein the peripheral circuit area further includes a second edge area opposite to the first edge area and a fourth metal pad on the second edge area, the fourth metal pad contacting the third metal pad, wherein the memory cell area further includes a third contact extending from the common source plate and connected to the third metal pad, and wherein the peripheral circuit area further includes a fourth contact extending from a second common source line switch and connected to the fourth metal pad.

4 . The nonvolatile memory device of claim 1 , wherein the first metal pad
and the second metal pad are formed of copper.

5 . The nonvolatile memory device of claim 1 , wherein the first metal pad and the second metal pad are connected by bonding manner.

6 . The nonvolatile memory device of claim 1 , wherein the memory cell area is formed on a first wafer and the peripheral circuit area is formed on a second wafer.

7 . The nonvolatile memory device of claim 1 , wherein the at least one cell structure is disposed between the common source plate and the middle area.

8 . The nonvolatile memory device of claim 7 , wherein the at least one cell structure comprises multiple cell structures spaced apart on the common source plate and separated by respective word line cuts.

9 . The nonvolatile memory device of claim 1 , wherein the first contact is directly connected between the common source plate and the first metal pad without a horizontal extension.

10 . The nonvolatile memory device of claim 1 , wherein the peripheral circuit area further includes a common source line driver in the first edge area, the common source line driver being connected to the common source line switch and providing a voltage to the common source plate.

11 . A nonvolatile memory device comprising:
a memory cell array including a plurality of cell strings disposed on a common source plate; and a peripheral circuit having an upper surface on which the memory cell array is mounted, wherein the peripheral circuit includes: a first row decoder configured to bias the plurality of cell strings through first contacts extending upward to first metal pads; a second row decoder configured to bias the plurality of cell strings through second contacts extending upward to second metal pads; a first common source switch configured to bias the common source plate through a third contact extending upward to a third metal pad; and a second common source switch configured to bias the common source plate through a fourth contact extending upward to a fourth metal pad.

12 . The nonvolatile memory device of claim 11 , wherein the memory cell array includes:
fifth contacts extending downward from word lines to fifth metal pads, the fifth metal pads contacting the first metal pads; sixth contacts extending downward from the word lines to sixth metal pads, the sixth metal pads contacting the second metal pads; a seventh contact extending downward from the common source plate to a seventh metal pad, the seventh metal pad contacting the third metal pad; and an eighth contact extending downward from the common source plate to an eighth metal pad, the eighth metal pad contacting the fourth metal pad.

13 . The nonvolatile memory device of claim 12 , wherein the first metal pads, the second metal pads, the third metal pad, the fourth metal pad, the fifth metal pads, the sixth metal pads, the seventh metal pad and the eighth metal pad are formed of copper.

14 . The nonvolatile memory device of claim 12 , wherein the first metal pads, the second metal pads, the third metal pad, the fourth metal pad are connected with the fifth metal pads, the sixth metal pads, the seventh metal pad and the eighth metal pad by bonding manner.

15 . The nonvolatile memory device of claim 12 , wherein the memory cell array is formed on a first wafer and the peripheral circuit is formed on a second wafer.

16 . The nonvolatile memory device of claim 12 , wherein the seventh contact is directly connected between the common source plate and the seventh metal pad without a horizontal extension.

17 . The nonvolatile memory device of claim 12 , wherein the eighth contact is directly connected between the common source plate and the eighth metal pad without a horizontal extension.

18 . The nonvolatile memory device of claim 11 , wherein the third contact is directly connected between the first common source switch and the third metal pad without a horizontal extension.

19 . The nonvolatile memory device of claim 11 , wherein the fourth contact is directly connected between the second common source switch and the fourth metal pad without a horizontal extension.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Dongha
• Lee Yohan

Classifications

• H10B41/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title