Three-dimensional semiconductor memory device including vertically stacked electrodes

Patent metadata

Field	Value
Publication number	US-10332902-B2
Application number	US-201715805513-A
Country	US
Kind code	B2
Filing date	Nov 7, 2017
Priority date	Oct 27, 2014
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure. At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device, comprising:
a metal silicide layer;
a silicon layer on a top surface of the metal silicide layer;
a stack structure comprising a plurality of electrodes vertically stacked on the silicon layer, and
a plurality of vertical structures penetrating the stack structure and connected to the silicon layer.

2. The 3D semiconductor memory device of claim 1 , further comprising a peripheral logic structure comprising peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer covering the peripheral logic circuits,
wherein the metal silicide layer is disposed on the first insulation layer.

3. The 3D semiconductor memory device of claim 2 , wherein the metal silicide layer is in direct contact with the first insulation layer.

4. The 3D semiconductor memory device of claim 2 , Wherein the peripheral logic structure further comprises at least two interconnections located at different levels from a top surface of the semiconductor substrate.

5. The 3D semiconductor memory device of claim 2 , wherein the peripheral logic circuits include a plurality of MOS transistors on the semiconductor substrate, and wherein the MOS transistors are overlapped with the metal silicide layer.

6. The 3D semiconductor memory device of claim 2 , wherein the peripheral logic circuits include a voltage generator disposed on the semiconductor substrate and electrically connected to the metal silicide layer.

7. The 3D semiconductor memory device of claim 1 , wherein the stack structure extends in a first direction on the silicon layer,
wherein the silicon layer includes a common source region disposed at a side of the stack structure, and
wherein the common source region has dopants of a first conductivity type.

8. The 3D semiconductor memory device of claim 1 , wherein the silicon layer has dopants of a second conductivity type,
wherein the silicon layer comprises:
a first portion in contact with the metal silicide layer; and
a second portion on the first portion, and.
wherein a concentration of the dopants of the second conductivity type in the first portion is higher than a concentration of the dopants of the second conductivity type in the second portion.

9. The 3D semiconductor memory device of claim 1 , wherein the silicon layer includes a well dopant region having a second conductivity type, and
wherein the well dopant region is in contact with the metal silicide layer.

10. The 3D semiconductor memory device of claim 1 , wherein each of the vertical structures comprises:
a vertical semiconductor layer connected to the silicon layer; and
a data storage layer disposed between the stack structure and the vertical semiconductor layer.

11. The 3D semiconductor memory device of claim 1 , further comprising a connection plug electrically connecting one of the electrodes with the peripheral logic structure.

12. The 3D semiconductor memory device of claim 1 , wherein the stack structure has a stepwise structure defined by end portions of the electrodes.

13. A three-dimensional (3D) semiconductor memory device, comprising:
a peripheral logic structure comprising peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer covering the peripheral logic circuits;
a metal silicide layer disposed on the peripheral logic structure;
a silicon layer on a top surface of the metal silicide layer;
a stack structure comprising a plurality of electrodes vertically stacked on the silicon layer, and
a plurality of vertical structures penetrating the stack structure and connected to the silicon layer.

14. The 3D semiconductor memory device of claim 13 , wherein the metal silicide layer and the silicon layer are overlapped with the peripheral logic structure.

15. The 3D semiconductor memory device of claim 13 , wherein the metal silicide layer is in direct contact with the first insulation layer.

16. The 3D semiconductor memory device of claim 13 , wherein the peripheral logic structure further comprises at least two interconnections located at different levels from a top surface of the semiconductor substrate, and
wherein the interconnections are electrically connected to the peripheral logic circuits.

17. The 3D semiconductor memory device of claim 13 , wherein the peripheral logic structure further comprises an interconnection structure for electrically connecting the metal silicide layer to the peripheral logic circuits.

18. The 3D semiconductor memory device of claim 13 , wherein the silicon layer has dopants of a second conductivity type,
wherein the silicon layer comprises: a first portion in contact with the metal silicide layer; and a second portion on the first portion, and
wherein a concentration of the dopants of the second conductivity type in the first portion is higher than a concentration of the dopants of the second conductivity type in the second portion.

19. The 3D semiconductor memory device of claim 13 , wherein the stack structure has a stepwise structure defined by end portions of the electrodes.

20. The 3D semiconductor memory device of claim 13 , further comprising a connection plug electrically connecting one of the electrodes with the peripheral logic structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Yunghwan
• Sim Jaesung
• Kang Shinhwan
• Park Youngwoo
• Lee Jaeduk

Classifications

• H10W90/00

  Package configurations · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11575 Primary

  Electricity · mapped topic

• H01L27/11517

  Electricity · mapped topic