Nonvolatile semiconductor memory device and memory system having the same

Patent metadata

Field	Value
Publication number	US-9418742-B2
Application number	US-201314039899-A
Country	US
Kind code	B2
Filing date	Sep 27, 2013
Priority date	Apr 22, 2010
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A nonvolatile semiconductor memory device includes a first string including a first number of memory cells connected in series each storing therein information in a nonvolatile manner; and a second string including a second number of memory cells connected in series each storing therein information in a nonvolatile manner, wherein the second number is smaller than the first number.

First claim

What is claimed is:

1. A memory system comprising:
a nonvolatile semiconductor memory unit;
and a controller,
wherein the nonvolatile semiconductor memory unit includes:
a first memory cell array including at least one first string group constituted of a plurality of first strings, each of the first strings including a first number of first memory cells each storing therein information in a nonvolatile manner, each of the first memory cells being connected to an associated one of a plurality of first word lines;
a second memory cell array including at least one second string group constituted of a plurality of second strings, each of the second strings including a second number of second memory cell or cells each storing therein information in a nonvolatile manner, the second number being smaller than the first number, each of the second memory cell or cells being connected to a second word line or an associated one of a plurality of second word lines;
a first bit line connected to one of the first strings;
a second bit line connected to one of the second strings; and
a page buffer that stores therein data read from the first and second memory cell arrays via the first and second bit lines, respectively,
wherein the controller controls access to the first and/or second memory cell arrays, the nonvolatile semiconductor memory unit further includes an external terminal connected to the controller, and
the controller controls a level of a signal supplied to the external terminal in response to selection of an access target between the first and second memory cell arrays.

2. The memory system as claimed in claim 1 , wherein
the nonvolatile semiconductor memory unit further includes a nonvolatile memory space where control information is stored,
the controller updates the control information, and
the nonvolatile semiconductor memory unit makes access to either one of the first and second memory cell arrays based on the control information.

3. The memory system as claimed in claim 1 , wherein the controller controls the nonvolatile semiconductor memory unit to initially make access to boot code data that boots the controller stored in the second memory cell array or an external system that controls the controller when a power is supplied to the memory system.

4. The memory system as claimed in claim 3 , wherein
the controller issues an instruction to access to the first memory cell array or the second memory cell array after making access to the boot code data, and
the nonvolatile semiconductor memory unit permits accessing to the first memory cell array or the second memory cell array after accessing to the boot code data.

5. The memory system as claimed in claim 1 , wherein
the nonvolatile semiconductor memory unit further includes a counter that counts a number of toggles of a signal supplied from an external terminal, and
the nonvolatile semiconductor memory unit permits accessing to the first memory cell array until the number of toggles reaches a predetermined number, and permits accessing to the second memory cell array after the number of toggles reaches the predetermined number.

6. The memory system as claimed in claim 1 , wherein
the nonvolatile semiconductor memory unit further includes a first I/F that is an external interface circuit for the first memory cell array, and a second I/F that is an external interface circuit for the second memory cell array,
the controller includes a first external interface circuit connected to the first I/F, and a second external interface circuit connected to the second I/F,
the controller sends an access command to the nonvolatile semiconductor memory unit through the first external interface circuit when accessing to the first memory cell array, and
the controller sends an access command to the nonvolatile semiconductor memory unit through the second external interface circuit when accessing to the second memory cell array.

Assignees

• Ps4 Luxco Sarl

Inventors

• Shinozaki Naoharu
• Taguchi Masao
• Hatada Takahiro
• Sugimoto Satoru
• Sakurakawa Satoshi

Classifications

• G11C16/22

  Safety or protection circuits preventing unauthorised or accidental access to memory cells · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G11C16/06 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title