Semiconductor memory device and method of operating the same

Patent metadata

Field	Value
Publication number	US-10020070-B2
Application number	US-201715416268-A
Country	US
Kind code	B2
Filing date	Jan 26, 2017
Priority date	Sep 23, 2016
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to control the memory cell array, the peripheral circuit including a first region disposed under the memory cell array and a second region; and a fall sensing unit configured to sense whether a failure has occurred in the first or the second regions.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells;
a peripheral circuit configured to control the memory cell array, the peripheral circuit including a first region disposed under the memory cell array and a second region; and
a fail sensing unit configured to sense whether a failure has occurred in the first or the second regions,
wherein the fail sensing unit comprises:
a latch unit configured to temporarily store data provided through the second region; and
a fail control unit configured to block data transfer between the first and second regions in response to a control signal,

wherein the fail sensing unit outputs the temporarily-stored data to the second region in response to a read command, and
wherein the failure is present in the second region when a response of the read command fails.

2. The semiconductor memory device of claim 1 , wherein the fail sensing unit is disposed between the first region and the second region.

3. The semiconductor memory device of claim 1 , wherein the fail sensing unit transfers data from the second region to the first region when the fail sensing unit is deactivated.

4. The semiconductor memory device of claim 1 , wherein the fail sensing unit temporarily stores data provided from the second region when the fail sensing unit is activated.

5. The semiconductor memory device of claim 1 , wherein the fail sensing unit blocks data transfer between the first and second regions when the fail sensing unit is activated.

6. The semiconductor memory device of claim 1 ,
wherein the fail sensing unit is activated and blocks data transfer between the first and second regions when the control signal has a first level, and
wherein the fail sensing unit is deactivated and transfers data between the first and second regions when the control signal has a second level.

7. The semiconductor memory device of claim 1 , wherein the failure is present in the first region when a response of the read command passes.

8. The semiconductor memory device of claim 1 , wherein the memory cell array is a three-dimensional nonvolatile memory cell array.

9. The semiconductor memory device of claim 1 , wherein the memory cell array is a flash memory array.

10. A method of operating a semiconductor memory device, including a memory cell array and a peripheral circuit having a first region disposed under the memory cell array and a second region and configured to control the memory cell array, the method comprising:
performing a first program operation to program first program data to selected memory cells included in the memory cell array;
performing a first read operation of reading data from a selected memory cell;
performing a second program operation to program second program data to the selected memory cells;
performing a second read operation for the selected memory cells; and
determining that the failure is present in the second region, when the second read operation fails.

11. The method of claim 10 , further comprising determining that the failure is present in the first region, when the second read operation passes.

12. The method of claim 10 , wherein the performing the first program operation comprises storing the first program data from the second region to the selected memory cells through the first region.

13. The method of claim 10 , wherein the performing the second program operation comprises temporarily storing the second program data in a latch disposed between the first and second regions.

Assignees

• Sk Hynix Inc

Inventors

• Choi Hoon

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C29/1201 Primary

  comprising I/O circuitry · CPC title

• G11C16/10

  Programming or data input circuits · CPC title