Nonvolatile memory device including multi-plane

Patent metadata

Field	Value
Publication number	US-2016163386-A1
Application number	US-201514817281-A
Country	US
Kind code	A1
Filing date	Aug 4, 2015
Priority date	Dec 8, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.

First claim

1 . A nonvolatile memory device comprising:
a first plane disposed on a first semiconductor layer and including first cell strings formed in a first direction orthogonal to the first semiconductor layer; a second plane disposed on a second semiconductor layer and including second cell strings formed in the first direction; a first address decoder configured to supply first operation voltages to the first plane; a second address decoder configured to supply second operation voltages to the second plane; a first peripheral circuit disposed between a substrate and the first semiconductor layer and configured to control the first address decoder; and a second peripheral circuit disposed between the substrate and the second semiconductor layer and configured to control the second address decoder, wherein the first peripheral circuit and second peripheral circuit are connected via a peripheral conductive layer disposed under the first semiconductor layer and second semiconductor layer.

2 . The nonvolatile memory device of claim 1 , further comprising:
a first page buffer circuit configured to program data to the first cell strings and read data from the first cell strings; a second page buffer circuit configured to program data to the second cell strings and read data from the second cell strings, wherein the first page buffer circuit is arranged adjacent to the first peripheral circuit on the substrate and the second page buffer circuit is arranged adjacent to the second peripheral circuit on the substrate.

3 . The nonvolatile memory device of claim 2 , wherein the first page buffer circuit is connected to a first page buffer line disposed under the semiconductor layer via a first page buffer contact, and to first bit lines connected to the first cell strings through a page buffer via penetrating the semiconductor layer.

4 . The nonvolatile memory device of claim 3 , wherein the first page buffer line is connect to a second page buffer line disposed under the semiconductor layer via a second page buffer contact, and to the first bit lines through the page buffer via.

5 . The nonvolatile memory device of claim 2 , wherein the first page buffer circuit is disposed under the first plane, and the second page buffer circuit is disposed under the second plane.

6 . The nonvolatile memory device of claim 2 , wherein the first page buffer circuit comprises a first sub-buffer group and a second sub-buffer group, and the first peripheral circuit is disposed between the first sub-buffer group and the second sub-buffer group.

7 . The nonvolatile memory device of claim 1 , further comprising:
a first page buffer circuit configured to program data to the first cell strings and read data from the first cell strings; a second page buffer circuit configured to program data to the second cell strings and read data from the second cell strings, the first page buffer circuit is disposed under the first plane, adjacent to a longitudinal section of the first plane, and connected to the first cell strings via first bit lines, the second page buffer circuit is disposed under the second plane, adjacent to a longitudinal section of the second plane, and connected to the second cell strings via second bit lines.

8 . The nonvolatile memory device of claim 1 , wherein the first plane and the second plane are disposed adjacent to each other,
the first address decoder is arranged around the first plane on a side opposite to that of the second plane, and the second address decoder is arranged around the second plane on a side opposite to that of the first plane.

9 . The nonvolatile memory device of claim 8 , further comprising:
an Input/Output (I/O) pad disposed along an orthogonal surface adjacent to a surface of at least one of the first plane and second plane, wherein the I/O pad is configured to transmit and receive at least one of a command and an address from an external device.

10 . The nonvolatile memory device of claim 1 , wherein the first peripheral circuit comprises a first decoder controller that controls the first address decoder, and the second peripheral circuit comprises a second decoder controller that controls the second address decoder.

11 . The nonvolatile memory device of claim 10 , wherein the first decoder controller is disposed adjacent to the first address decoder, and the second decoder controller is disposed adjacent to the second address decoder.

12 . The nonvolatile memory device of claim 1 , wherein each one of the first peripheral circuit and the second peripheral circuit comprises:
a voltage generator that generates the first operation voltages and second operation voltages and provides the first and second operation voltages to the first address decoder and second address decoder; and control logic configured to control the voltage generator, the first address decoder and second address decoder.

13 . The nonvolatile memory device of claim 12 , wherein each one the first peripheral circuit and second peripheral circuit comprise:
an Input/Output (I/O) circuit configured to receive a command, an address, and write data from the an external device, transmit the command to the control logic, transmit the address to the first address decoder and the second address decoder according to a control of the control logic, and transmit the write data to a first page buffer and a second page buffer connected respectively to the first plane and the second plane via a plurality of bit lines.

14 . The nonvolatile memory device of claim 13 , wherein the first page buffer circuit and second page buffer circuit are respectively configured to read data from the first plane and second plane under control of the control logic, and
the I/O circuit is further configured to transmit a data read respectively from the first plane and second plane.

15 . The nonvolatile memory device of claim 14 , wherein the control logic is disposed between the voltage generator and the I/O circuit.

16 . The nonvolatile memory device of claim 14 , wherein the voltage generator and the I/O circuit are disposed adjacent to each other, and
the control logic is arranged adjacent to an orthogonal surface adjacent to the voltage generator and the I/O circuit.

17 . The nonvolatile memory device of claim 1 , wherein the peripheral conductive layer comprises:
a first peripheral conductive line connected to an active region disposed on the substrate via a first peripheral contact; a second peripheral conductive line connected to the first peripheral conductive line via a second peripheral contact; a third peripheral conductive line connected to the second peripheral conductive line via a third peripheral contact, wherein the first peripheral circuit and second peripheral circuit are connected each other via the third peripheral conductive line.

18 . The nonvolatile memory device of claim 17 , wherein the active region includes at least one transistor included in the first peripheral circuit connected to a gate region of at least one transistor included in the second peripheral circuit via at least one of the first contact, second contact, third contact, first peripheral conductive line, second peripheral conductive line and third peripheral conductive line.

19 . The nonvolatile memory device of claim 1 , wherein the first address decoder is connected to the first cell strings via first word lines, the second address decoder is connected the second cell strings via second word lines, and
each of the first word lines and second word lines i

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Chul-Jin
• Kwak Pansuk
• Ryu Younghwan

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C8/10

  Decoders · CPC title